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1. 发明公开

EP3504629A1 ENHANCE MEMORY ACCESS PERMISSION BASED ON PER-PAGE CURRENT PRIVILEGE LEVEL 有权
公开(公告)号：EP3504629A1
公开(公告)日：2019-07-03
申请号：EP17847142.1
申请日：2017-07-21
申请人： Intel Corporation
发明人： HILDESHEIM, Gur , NEIGER, Gilbert , PATEL, Baiju V. , RAIS, Ron
IPC分类号： G06F12/14

2. 发明公开

EP3314853A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO SUPPORT LIVE MIGRATION OF PROTECTED CONTAINERS 有权
标题翻译：处理器，方法，系统和说明，以支持受保护的容器的实时迁移
公开(公告)号：EP3314853A1
公开(公告)日：2018-05-02
申请号：EP16814991.2
申请日：2016-05-27
申请人： Intel Corporation
发明人： ROZAS, Carlos V. , VIJ, Mona , LESLIE-HURD, Rebekah M. , ZMUDZINSKI, Krystof C. , CHAKRABARTI, Somnath , MCKEEN, Francis X. , SCARLATA, Vincent R. , JOHNSON, Simon P. , ALEXANDROVICH, Ilya , NEIGER, Gilbert , SHANBHOGUE, Vedvyas , ANATI, Ittai
IPC分类号： H04L29/06 , H04L9/08 , H04L29/08
CPC分类号： G06F12/1408 , G06F8/41 , G06F9/30145 , G06F9/45558 , G06F21/53 , G06F21/602 , G06F2009/4557 , G06F2009/45587 , G06F2212/1052
摘要： A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.

3. 发明公开

EP3238084A1 DELIVERING INTERRUPTS TO USER-LEVEL APPLICATIONS 审中-公开
标题翻译：向用户级应用程序提供中断
公开(公告)号：EP3238084A1
公开(公告)日：2017-11-01
申请号：EP15873910.2
申请日：2015-11-12
申请人： Intel Corporation
发明人： NEIGER, Gilbert , SANKARAN, Rajesh, M.
IPC分类号： G06F13/24 , G06F13/16
CPC分类号： G06F13/34
摘要： Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.
摘要翻译：向用户级应用程序提供中断的系统和方法。一种示例处理系统包括：存储器，被配置为存储与由处理系统执行的多个用户级应用对应的多个用户级APIC数据结构和多个用户级中断处理机地址数据结构; 以及处理内核，被配置为响应于接收到用户级中断的通知，设置待定中断位标志，所述待决中断位标志具有由与用户级中断相关联的用户级APIC数据结构中的用户级中断的标识符定义的位置由处理核心当前正在执行的用户级应用程序，并且调用由与用户级应用程序相关联的用户级中断处理程序地址数据结构标识的用户级中断处理程序，用于具有用户级APIC数据结构所标识的一个或多个未决用户级中断中的最高优先级。

4. 发明公开

EP4302183A1 FLEXIBLE RETURN AND EVENT DELIVERY 审中-公开
公开(公告)号：EP4302183A1
公开(公告)日：2024-01-10
申请号：EP22763906.9
申请日：2022-03-01
申请人： INTEL Corporation
发明人： NEIGER, Gilbert , ANVIN, H. Peter , SHANBHOGUE, Vedvyas , GUPTA, Deepak
IPC分类号： G06F9/30 , G06F9/48 , G06F11/14

5. 发明公开

EP4089531A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 审中-实审
公开(公告)号：EP4089531A1
公开(公告)日：2022-11-16
申请号：EP22180798.5
申请日：2016-12-31
申请人： Intel Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/38 , G06F12/08
摘要： The present disclosure provides an apparatus comprising an accelerator; a local memory comprising a plurality of stacked dynamic random access memory, DRAM, dies; a silicon bridge to couple the accelerator to the plurality of stacked DRAM dies, wherein connections between the accelerator and the plurality of stacked DRAM dies run through the silicon bridge. The accelerator comprising a plurality of processing elements to perform processing tasks allocated by an external processor; a cache coherent interface to couple the accelerator to the external processor, the cache coherent interface to ensure that data stored in the local memory and/or an accelerator cache is coherent with data stored in a system memory and caches of the external processor; and logic to map a virtual memory space to heterogeneous forms of physical system memory including the local memory and the system memory, the accelerator and the external processor to both use the virtual memory space to access corresponding portions of the local memory and the system memory.

6. 发明公开

EP3905039A1 VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM 审中-公开
公开(公告)号：EP3905039A1
公开(公告)日：2021-11-03
申请号：EP21163280.7
申请日：2006-01-10
申请人： INTEL Corporation
发明人： BENNETT, Steven , ANDERSON, Andrew , NEIGER, Gilbert , SANKARAN, Rajesh , SMITH, Larry , UHLIG, Richard , RODGERS, Dion
IPC分类号： G06F9/455 , G06F12/109
摘要： A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

7. 发明公开

EP3761210A1 CRYPTOGRAPHIC COMPUTING USING ENCRYPTED BASE ADDRESSES AND USED IN MULTI-TENANT ENVIRONMENTS 有权
公开(公告)号：EP3761210A1
公开(公告)日：2021-01-06
申请号：EP20168972.6
申请日：2020-03-17
申请人： Intel Corporation
发明人： NEIGER, Gilbert , DURHAM, David M , BRANDT, Jason , LEMAY, Michael , JAYARAM MASTI, Ramya
IPC分类号： G06F21/79 , G06F12/02 , G06F21/60 , G06F21/78
摘要： Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

8. 发明公开

EP3572937A1 VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM 有权
公开(公告)号：EP3572937A1
公开(公告)日：2019-11-27
申请号：EP19160715.9
申请日：2006-01-10
申请人： Intel Corporation
发明人： BENNETT, Steven , ANDERSON, Andrew , NEIGER, Gilbert , SANKARAN, Rajesh , SMITH, Larry , UHLIG, Richard , ROGERS, Dion
IPC分类号： G06F9/455
摘要： A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

9. 发明授权

EP3210123B1 MEMORY PROTECTION KEY ARCHITECTURE WITH INDEPENDENT USER AND SUPERVISOR DOMAINS 有权
公开(公告)号：EP3210123B1
公开(公告)日：2019-07-03
申请号：EP15851712.8
申请日：2015-08-19
申请人： Intel Corporation
发明人： KOUFATY, David, A. , NEIGER, Gilbert , SANKARAN, Rajesh, M. , ANDERSON, Andrew, V. , DULLOOR, Subramanya, R. , HAAS, Werner , NUZMAN, Joseph
IPC分类号： G06F12/14 , G06F12/10 , G06F21/52

10. 发明公开

EP3198402A1 AVOIDING PREMATURE ENABLING OF NONMASKABLE INTERRUPTS WHEN RETURNING FROM EXCEPTIONS 有权
标题翻译：避免早期从例外返回时启用无法中断的中断
公开(公告)号：EP3198402A1
公开(公告)日：2017-08-02
申请号：EP15843881.2
申请日：2015-08-31
申请人： Intel Corporation
发明人： ANVIN, H. Peter , NEIGER, Gilbert
IPC分类号： G06F9/30
CPC分类号： G06F13/24 , G06F9/327 , G06F9/4812 , G11C7/1072
摘要： A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.
摘要翻译：一个方面的处理器包括用于解码异常处理程序返回指令的解码单元。处理器还包括与解码单元耦合的异常处理程序返回执行单元。响应于异常处理程序返回指令，异常处理程序返回执行单元将不配置处理器以使得能够在NMI处理程序将后续接收到的不可屏蔽中断（NMI）传递给NMI处理程序，如果与异常处理程序返回指令相对应的异常，在NMI处理程序内被采取。响应于异常处理程序返回指令，异常处理程序返回执行单元将配置处理器，以使得如果在NMI处理程序中未采取异常，则能够将随后接收到的NMI传送到NMI处理程序。公开了其他处理器，方法，系统和指令。

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