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1. 发明授权

EP3326986B1 PROCESS FOR THE MANUFACTURE OF A METAL-CERAMIC SUBSTRATE 有权
公开(公告)号：EP3326986B1
公开(公告)日：2020-11-25
申请号：EP16200876.7
申请日：2016-11-28
申请人： Infineon Technologies AG
发明人： ROTH, Alexander
IPC分类号： C04B37/02 , H01L21/48 , H01L23/373 , C04B37/00 , C04B35/645 , B32B15/00 , B32B18/00 , B33Y10/00 , H01L23/15

2. 发明公开

EP4273928A1 A SEMICONDUCTOR PACKAGE COMPRISING POWER AND LOGIC ON A SINGLE CERAMIC PLATE 审中-实审
公开(公告)号：EP4273928A1
公开(公告)日：2023-11-08
申请号：EP22171175.7
申请日：2022-05-02
申请人： Infineon Technologies AG
发明人： ROTH, Alexander
IPC分类号： H01L25/16 , H01L23/373 , H01L23/433 , H01L23/492
摘要： A semiconductor package (10; 20; 30) comprising a ceramic plate 1, a first conductive layer (2) disposed on the ceramic plate 1, the first conductive layer (2) comprising a first portion (2.1) and a second portion (2.2), a semiconductor transistor die (3) disposed above the first portion (2.1) of the first conductive layer (2), an electrical connector (4) disposed between the semiconductor transistor die (3) and the first portion (2.1) of the first conductive layer (2), a semiconductor logic die (5) disposed on the second portion (2.2) of the first conductive layer (2), and an encapsulant (6) covering at least in part the ceramic plate (1), the first conductive layer (2), the semiconductor transistor die (3) and the semiconductor logic die (5).

3. 发明公开

EP3326990A1 RESIN-IMPREGNATED BORON NITRIDE BODY AND A METHOD FOR PRODUCING THE SAME 有权
公开(公告)号：EP3326990A1
公开(公告)日：2018-05-30
申请号：EP17200378.2
申请日：2017-11-07
申请人： Infineon Technologies AG
发明人： ROTH, Alexander
IPC分类号： C04B41/83 , H01L23/373
CPC分类号： C09K5/14 , C04B41/009 , C04B41/4853 , C04B41/4961 , C04B41/83 , C04B41/84 , C04B2111/00844 , C08J5/24 , C08J7/08 , C08J2363/00 , C08J2383/04 , C08K3/38 , C08K2003/385 , C08K2201/001 , H01L23/3737 , C04B35/583 , C04B38/06
摘要： A resin-impregnated boron nitride body comprising polymer-derived boron nitride and a resin is provided. In addition, a process for manufacturing such a resin-impregnated boron nitride body comprising the steps:
(a) polymerizing a boron nitride molecular precursor into a preceramic polymer,
(b) shaping the preceramic polymer to form an infusible polymer body,
(c) submitting the polymer body to a thermal treatment,
(d) impregnating the obtained boron nitride body with a resin, and
(e) curing of the resin
is disclosed.

4. 发明公开

EP3326986A1 PROCESS FOR THE MANUFACTURE OF A METAL-CERAMIC SUBSTRATE 有权
公开(公告)号：EP3326986A1
公开(公告)日：2018-05-30
申请号：EP16200876.7
申请日：2016-11-28
申请人： Infineon Technologies AG
发明人： ROTH, Alexander
IPC分类号： C04B37/02 , B32B18/00 , B32B15/00 , C04B35/645 , C04B37/00 , H01L23/373 , H01L21/48
CPC分类号： C04B37/021 , B32B15/00 , B32B18/00 , C04B35/645 , C04B35/6455 , C04B37/026 , C04B2235/5445 , C04B2235/6026 , C04B2235/6584 , C04B2235/6587 , C04B2235/9623 , C04B2237/343 , C04B2237/366 , C04B2237/368 , C04B2237/402 , C04B2237/407 , C04B2237/54 , C04B2237/568 , C04B2237/78 , C04B2237/84 , H01L21/4803 , H01L21/4807 , H01L21/481 , H01L21/4846 , H01L21/4857 , H01L23/15 , H01L23/3735
摘要： The invention relates to a process for the manufacture of a metal-ceramic substrate (2, 12, 15), comprising at least the following steps:
- forming a metal-ceramic assembly (3, 19) of an at least partially non-sintered ceramic material (4) and at least an oxidized metal body (5), which at least partially is in contact with the ceramic material (4);
- sintering the ceramic material (4) of the metal-ceramic assembly (3, 19) at a sintering temperature below a bonding temperature of the metal body (5) and under a sintering pressure higher than the atmospheric air pressure for a predictable sintering period to form a ceramic body (11) from the ceramic material (4);
- bonding the metal body (5) of the metal-ceramic assembly (3, 19) to the sintered ceramic body (11) at bonding temperature for a predictable bonding period to form the metal-ceramic substrate (2, 12, 15); and
- cooling the metal-ceramic substrate (2, 12, 15) to room temperature.

5. 发明公开

EP3326989A1 RESIN-IMPREGNATED BORON NITRIDE BODY AND A METHOD FOR PRODUCING THE SAME 审中-公开
公开(公告)号：EP3326989A1
公开(公告)日：2018-05-30
申请号：EP16200875.9
申请日：2016-11-28
申请人： Infineon Technologies AG
发明人： ROTH, Alexander
IPC分类号： C04B41/83 , H01L23/373
CPC分类号： C09K5/14 , C04B41/009 , C04B41/4853 , C04B41/4961 , C04B41/83 , C04B41/84 , C04B2111/00844 , C08J5/24 , C08J7/08 , C08J2363/00 , C08J2383/04 , C08K3/38 , C08K2003/385 , C08K2201/001 , H01L23/3737 , C04B35/583 , C04B38/06
摘要： A resin-impregnated boron nitride body comprising polymer-derived boron nitride and a resin is provided. In addition, a process for manufacturing such a resin-impregnated boron nitride body comprising the steps:
(a) polymerizing a boron nitride molecular precursor into a preceramic polymer,
(b) shaping the preceramic polymer to form an infusible polymer body,
(c) submitting the polymer body to a thermal treatment,
(d) impregnating the obtained boron nitride body with a resin, and
(e) curing of the resin
is disclosed.

6. 发明公开

EP4401126A2 POWER SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME 审中-实审
公开(公告)号：EP4401126A2
公开(公告)日：2024-07-17
申请号：EP24171908.7
申请日：2018-01-30
申请人： Infineon Technologies AG
发明人： ROTH, Alexander , HOHLFELD, Olaf
IPC分类号： H01L23/24
CPC分类号： H01L23/053 , H01L21/54 , H01L23/562 , H01L2224/29120130101 , H01L2224/2913920130101 , H01L2224/3222520130101 , H01L2224/838420130101 , H01L2224/8385120130101 , H01L2924/1305520130101 , H01L2924/1306220130101 , H01L2924/1306420130101 , H01L2924/1309120130101 , H01L2924/1615120130101 , H01L2924/1625120130101 , H01L2924/181520130101 , H01L23/24
摘要： A power semiconductor module arrangement comprises a housing, a substrate arranged in the housing, the substrate comprising a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, at least one semiconductor body mounted on a first surface of the first metallization layer, at least one connecting element arranged on and electrically connected to the first surface of the first metallization layer, at least one contact element, wherein each of the at least one contact element is inserted into and electrically connected to one of the at least one connecting element, wherein each of the at least one contact element extends from the respective connecting element through the interior of the housing and to the outside of the housing in a direction perpendicular to the first surface, and a hard encapsulation that is arranged adjacent to the first metallization layer and that at least partly fills the inside of the housing, wherein the hard encapsulation has a hardness of at least 40 Shore A, each of the at least one contact element is partly embedded in the hard encapsulation, the hard encapsulation completely covers the at least one semiconductor body and any other components mounted on the substrate, each of the at least one contact element has a first length between the substrate and a cover of the housing in a direction perpendicular to the first surface of the first metallization layer, the hard encapsulation has a first thickness in a direction perpendicular to the first surface of the first metallization layer in areas surrounding each of the at least one contact element, the hard encapsulation has a second thickness in a direction perpendicular to the first surface of the first metallization layer in other areas, and the first thickness is greater than the second thickness.

7. 发明公开

EP4401126A3 POWER SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME 审中-实审
公开(公告)号：EP4401126A3
公开(公告)日：2024-09-25
申请号：EP24171908.7
申请日：2018-01-30
申请人： Infineon Technologies AG
发明人： ROTH, Alexander , HOHLFELD, Olaf
IPC分类号： H01L23/053 , H01L23/24 , H01L21/54
CPC分类号： H01L23/053 , H01L21/54 , H01L23/562 , H01L2224/29120130101 , H01L2224/2913920130101 , H01L2224/3222520130101 , H01L2224/838420130101 , H01L2224/8385120130101 , H01L2924/1305520130101 , H01L2924/1306220130101 , H01L2924/1306420130101 , H01L2924/1309120130101 , H01L2924/1615120130101 , H01L2924/1625120130101 , H01L2924/181520130101 , H01L23/24
摘要： A power semiconductor module arrangement comprises a housing, a substrate arranged in the housing, the substrate comprising a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, at least one semiconductor body mounted on a first surface of the first metallization layer, at least one connecting element arranged on and electrically connected to the first surface of the first metallization layer, at least one contact element, wherein each of the at least one contact element is inserted into and electrically connected to one of the at least one connecting element, wherein each of the at least one contact element extends from the respective connecting element through the interior of the housing and to the outside of the housing in a direction perpendicular to the first surface, and a hard encapsulation that is arranged adjacent to the first metallization layer and that at least partly fills the inside of the housing, wherein the hard encapsulation has a hardness of at least 40 Shore A, each of the at least one contact element is partly embedded in the hard encapsulation, the hard encapsulation completely covers the at least one semiconductor body and any other components mounted on the substrate, each of the at least one contact element has a first length between the substrate and a cover of the housing in a direction perpendicular to the first surface of the first metallization layer, the hard encapsulation has a first thickness in a direction perpendicular to the first surface of the first metallization layer in areas surrounding each of the at least one contact element, the hard encapsulation has a second thickness in a direction perpendicular to the first surface of the first metallization layer in other areas, and the first thickness is greater than the second thickness.

8. 发明公开

EP4414122A1 SOLDERABLE ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：EP4414122A1
公开(公告)日：2024-08-14
申请号：EP23155396.7
申请日：2023-02-07
申请人： Infineon Technologies AG
发明人： ROTH, Alexander , WATERLOO, Andreas
IPC分类号： B23K35/02 , H01L23/00 , B23K1/00
CPC分类号： B23K35/0244 , H01L24/83 , B23K1/0016 , H01L24/32 , H01L24/27 , H01L24/29
摘要： A solderable electronic device comprises a base comprising one or more of a semiconductor die and a power electronic substrate, a first layer arranged over the base, the first layer comprising a solid reducing agent, and a solder preform arranged over the first layer, wherein the reducing agent is configured to reduce a solder material of the solder preform during a soldering process.

9. 发明公开

EP3951842A3 PRE-PLATING OF SOLDER LAYER ON SOLDERABLE ELEMENTS FOR DIFFUSION SOLDERING, CORRESPONDING CIRCUIT CARRIER AND CORRESPONDING METHOD OF SOLDERING ELECTRONIC COMPONENTS 无效
公开(公告)号：EP3951842A3
公开(公告)日：2022-07-06
申请号：EP21187715.4
申请日：2021-07-26
申请人： Infineon Technologies AG
发明人： HEINRICH, Alexander , ROTH, Alexander
IPC分类号： H01L21/60 , H01L23/488 , H01L23/498 , H05K3/34 , B23K1/19
摘要： A pre-soldered circuit carrier (100) includes a carrier having a metal die attach surface (108, 132, 140), a plated solder region (114) on the metal die attach surface (108, 132, 140), wherein a maximum thickness of the plated solder region (114) is at most 50 µm, the plated solder region (114) has a lower melting point than the die attach surface (108, 132, 140), and the plated solder region (114) forms one or more intermetallic phases (122) with the die attach surface (108, 132, 140) at a soldering temperature that is above the melting point of the plated solder region (114).
A method of forming a pre-soldered element comprises: providing a substrate (100) comprising a first metal joining surface (108, 132, 140); depositing a mask material (110) on the substrate (100) that covers the first metal joining surface (108, 132, 140); patterning the mask material (110) to form an opening (112) that exposes the first metal joining surface (108, 132, 140); and performing a plating process (e.g., an electroplating process or an electroless plating process) that forms a plated solder region (114) on a portion of the first metal joining surface (108, 132, 140) that is exposed by the opening (112); wherein the plated solder region (114) has a lower melting point than the first metal joining surface (108, 132, 140), and wherein the plated solder region (114) forms one or more intermetallic phases (122) with the first metal joining surface (108, 132, 140) at a soldering temperature that is above the melting point of the plated solder region (114), wherein a maximum thickness of the plated solder region (114) may be at most 50 µm.
A method of soldering electronic components comprises: providing a substrate (100) comprising a first metal joining surface (132) and a joining partner (116, 124, 126, 128) comprising a second metal joining surface, the substrate (100) or the joining partner (116, 124, 126, 128) being pre-plated with a plated solder region (114); arranging the joining partner (116, 124, 126, 128) and the substrate (100) together such that the plated solder region (114) interfaces with the first metal joining surface (132) and with the second metal joining surface; and performing a pressure-free diffusion soldering step that forms a first soldered joint (120, 136) between the first and second metal joining surfaces and the plated solder region (114), wherein a maximum thickness of the plated solder region is at most 50 µm, and wherein the soldering step is performed at a soldering temperature that causes the plated solder region (114) to melt and react with the first and second metal joining surfaces to form one or more intermetallic phases (122) within the first soldered joint (120, 136), each of the one or more intermetallic phases (122) having a melting point above the plated solder region (114) and the soldering temperature.
The pre-soldered circuit carrier or substrate (100) may comprise a dielectric layer (102) and a metal layer (104) attached to the dielectric layer (102), the metal layer (104) comprising one or more bond pads (106), wherein the die attach surface (108) is from one of the one or more bond pads (106). Alternatively, the pre-soldered circuit carrier or substrate (100) may be a leadframe comprising a die pad (130), wherein the die pad (130) comprises the die attach surface (132). Still alternatively, the substrate (100) may be a metal clip (134), wherein the first metal joining surface (140) is a die attach surface of the metal clip (134). The joining partner may be a semiconductor die (116, 124, 126), a passive electrical component or a mechanical connector (128). The plating step and the diffusion soldering step for the mechanical connectors (128) and first and second semiconductor dies (124, 126) may be performed simultaneously such that these soldered connections are formed at the same time. Alternatively, the soldered connections between the mechanical connectors (128) and the substrate (100) may be provided by a separate soldering process, which may involve conventional soldering techniques, e.g. by applying a solder paste and reflowing the solder paste and which can be performed at a temperature that is sufficient to reflow the solder for the mechanical connectors (128) but below the melting point of the intermetallic phases (122) present within the first soldered joints (120).

10. 发明公开

EP3951842A2 PRE-PLATING OF SOLDER LAYER ON SOLDERABLE ELEMENTS FOR DIFFUSION SOLDERING, CORRESPONDING CIRCUIT CARRIER AND CORRESPONDING METHOD OF SOLDERING ELECTRONIC COMPONENTS 无效
公开(公告)号：EP3951842A2
公开(公告)日：2022-02-09
申请号：EP21187715.4
申请日：2021-07-26
申请人： Infineon Technologies AG
发明人： HEINRICH, Alexander , ROTH, Alexander
IPC分类号： H01L21/60 , H01L23/488 , H01L23/498 , H05K3/34 , B23K1/19
摘要： A pre-soldered circuit carrier (100) includes a carrier having a metal die attach surface (108, 132, 140), a plated solder region (114) on the metal die attach surface (108, 132, 140), wherein a maximum thickness of the plated solder region (114) is at most 50 µm, the plated solder region (114) has a lower melting point than the die attach surface (108, 132, 140), and the plated solder region (114) forms one or more intermetallic phases (122) with the die attach surface (108, 132, 140) at a soldering temperature that is above the melting point of the plated solder region (114).
A method of forming a pre-soldered element comprises: providing a substrate (100) comprising a first metal joining surface (108, 132, 140); depositing a mask material (110) on the substrate (100) that covers the first metal joining surface (108, 132, 140); patterning the mask material (110) to form an opening (112) that exposes the first metal joining surface (108, 132, 140); and performing a plating process (e.g., an electroplating process or an electroless plating process) that forms a plated solder region (114) on a portion of the first metal joining surface (108, 132, 140) that is exposed by the opening (112); wherein the plated solder region (114) has a lower melting point than the first metal joining surface (108, 132, 140), and wherein the plated solder region (114) forms one or more intermetallic phases (122) with the first metal joining surface (108, 132, 140) at a soldering temperature that is above the melting point of the plated solder region (114), wherein a maximum thickness of the plated solder region (114) may be at most 50 µm.
A method of soldering electronic components comprises: providing a substrate (100) comprising a first metal joining surface (132) and a joining partner (116, 124, 126, 128) comprising a second metal joining surface, the substrate (100) or the joining partner (116, 124, 126, 128) being pre-plated with a plated solder region (114); arranging the joining partner (116, 124, 126, 128) and the substrate (100) together such that the plated solder region (114) interfaces with the first metal joining surface (132) and with the second metal joining surface; and performing a pressure-free diffusion soldering step that forms a first soldered joint (120, 136) between the first and second metal joining surfaces and the plated solder region (114), wherein a maximum thickness of the plated solder region is at most 50 µm, and wherein the soldering step is performed at a soldering temperature that causes the plated solder region (114) to melt and react with the first and second metal joining surfaces to form one or more intermetallic phases (122) within the first soldered joint (120, 136), each of the one or more intermetallic phases (122) having a melting point above the plated solder region (114) and the soldering temperature.
The pre-soldered circuit carrier or substrate (100) may comprise a dielectric layer (102) and a metal layer (104) attached to the dielectric layer (102), the metal layer (104) comprising one or more bond pads (106), wherein the die attach surface (108) is from one of the one or more bond pads (106). Alternatively, the pre-soldered circuit carrier or substrate (100) may be a leadframe comprising a die pad (130), wherein the die pad (130) comprises the die attach surface (132). Still alternatively, the substrate (100) may be a metal clip (134), wherein the first metal joining surface (140) is a die attach surface of the metal clip (134). The joining partner may be a semiconductor die (116, 124, 126), a passive electrical component or a mechanical connector (128). The plating step and the diffusion soldering step for the mechanical connectors (128) and first and second semiconductor dies (124, 126) may be performed simultaneously such that these soldered connections are formed at the same time. Alternatively, the soldered connections between the mechanical connectors (128) and the substrate (100) may be provided by a separate soldering process, which may involve conventional soldering techniques, e.g. by applying a solder paste and reflowing the solder paste and which can be performed at a temperature that is sufficient to reflow the solder for the mechanical connectors (128) but below the melting point of the intermetallic phases (122) present within the first soldered joints (120).

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