A power semiconductor module arrangement comprises a housing, a substrate arranged in the housing, the substrate comprising a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, at least one semiconductor body mounted on a first surface of the first metallization layer, at least one connecting element arranged on and electrically connected to the first surface of the first metallization layer, at least one contact element, wherein each of the at least one contact element is inserted into and electrically connected to one of the at least one connecting element, wherein each of the at least one contact element extends from the respective connecting element through the interior of the housing and to the outside of the housing in a direction perpendicular to the first surface, and a hard encapsulation that is arranged adjacent to the first metallization layer and that at least partly fills the inside of the housing, wherein the hard encapsulation has a hardness of at least 40 Shore A, each of the at least one contact element is partly embedded in the hard encapsulation, the hard encapsulation completely covers the at least one semiconductor body and any other components mounted on the substrate, each of the at least one contact element has a first length between the substrate and a cover of the housing in a direction perpendicular to the first surface of the first metallization layer, the hard encapsulation has a first thickness in a direction perpendicular to the first surface of the first metallization layer in areas surrounding each of the at least one contact element, the hard encapsulation has a second thickness in a direction perpendicular to the first surface of the first metallization layer in other areas, and the first thickness is greater than the second thickness.