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1. 发明公开

EP3789343A1 ISOLATED VERTICAL NANOWIRE 审中-公开
公开(公告)号：EP3789343A1
公开(公告)日：2021-03-10
申请号：EP19195803.2
申请日：2019-09-06
申请人： Imec VZW
发明人： HIBLOT, Gaspard , BAUDOT, Sylvain
IPC分类号： B82Y10/00 , H01L27/06 , H01L29/06 , H01L29/10 , H01L29/66 , H01L29/775 , H01L21/822 , H01L21/8234
摘要： A method for electrically isolating a vertical nanowire (210) on at least one location in the nanowire. The method comprises providing a substrate (200), forming a vertical nanowire stack on the substrate (200). The stack comprises at least one nanowire section (211) of a first material. A sacrificial section (212) of a second material is provided in the vertical nanowire stack on the at least one location. The second material is selected such that it can be selectively removed with respect to the first material. The method, moreover, comprises creating at least one interconnect (214) to the at least one nanowire section (211) which should be isolated, removing the at least one sacrificial section (212) and replacing it with an isolating section (213) after creating the interconnect (214). In the same way also to vertically spaced vertical nanowires (211) may be isolated.

2. 发明公开

EP4391032A1 INTEGRATED CIRCUIT CHIPS COMPRISING FORKSHEET DEVICES CONNECTED WITH BURIED POWER RAILS 审中-公开
公开(公告)号：EP4391032A1
公开(公告)日：2024-06-26
申请号：EP22216298.4
申请日：2022-12-23
申请人： Imec VZW
发明人： CHAN, Boon Teik , HIBLOT, Gaspard , MIRABELLI, Gioele
IPC分类号： H01L21/768 , H01L21/8238 , H01L23/528 , H01L23/535 , H01L29/775
CPC分类号： H01L29/775 , H01L21/76897 , H01L23/5286 , H01L23/535 , H01L21/823481 , H01L21/823475
摘要： A method comprising providing (901) a semiconductor substrate, forming (902) a device layer (2) comprising a forksheet device (30) on the substrate and providing the substrate (1) with a substrate part (31) of a dielectric wall (3) of the forksheet device (30), a first shallow trench isolation (41) and a second shallow trench isolation (42), wherein an extending part (411) of the first shallow trench isolation (41) comprises a first surface (410) facing a second surface (420) of an extending part (421) of the second shallow trench isolation (42), wherein a region (100) between the first surface (410) and the second surface (420) comprises a substrate material (120), and a via (51), filled with a via material (510), contacting a source or drain contact (21) and extending into the substrate (1) between the first shallow trench isolation (41) and the dielectric wall (3), then removing (903) the substrate material (120) so as to expose an end (311) of the dielectric wall (3), the first surface (410), and the second surface (420), then obtaining (904) a first spacer (61) and a second spacer (62), so as to obtain a trench (122), wherein the end of the dielectric wall (3) is exposed to the trench (122), then depositing (905) an electrically insulating material in the trench (122) so as to form an extension (7).

3. 发明公开

EP4386841A1 A SEMICONDUCTOR DEVICE STRUCTURE 审中-公开
公开(公告)号：EP4386841A1
公开(公告)日：2024-06-19
申请号：EP22214407.3
申请日：2022-12-18
申请人： Imec VZW
发明人： HIBLOT, Gaspard , JUSSOT, Julien
IPC分类号： H01L27/02 , H01L27/092 , H01L21/8234 , H01L29/775 , H10B10/00
CPC分类号： H01L27/0207 , H01L27/092 , H10B10/12 , H01L29/775 , H01L21/823814 , H01L21/823828
摘要： The disclosure relates to a semiconductor device structure. The device structure comprises a first and second FETs, each comprising respective S/D structures, a respective channel structure and a respective gate structure. Each S/D structure comprises a S/D body and a set of vertically spaced apart S/D prongs protruding laterally from the S/D body. The S/D prongs of the first and second FETs extend in opposite lateral directions. Each gate structure comprises a gate body and a set of gate prongs protruding laterally from the gate body into spaces between channel layers of the respective channel structures. The gate prongs of the first and second FETs extend in opposite lateral directions. Further, the gate prongs and S/D prongs of the first FET extend in opposite lateral directions, and the gate prongs and S/D prongs of the second FET extend in opposite lateral directions. A S/D body of the first FET device is arranged between the S/D bodies of the second FET device and a S/D body of the second FET device is arranged between the S/D bodies of the first FET device.

4. 发明公开

EP4167275A1 A METHOD FOR FORMING AN INTERCONNECTION STRUCTURE 审中-实审
公开(公告)号：EP4167275A1
公开(公告)日：2023-04-19
申请号：EP21203176.9
申请日：2021-10-18
申请人： Imec VZW
发明人： HIBLOT, Gaspard
IPC分类号： H01L21/768 , H01L21/822 , H01L23/528 , H01L23/535
摘要： A method for forming an interconnection structure for a first transistor and a second transistor is provided, wherein the first transistor includes a horizontally extending first channel portion (112) and the second transistor includes a horizontally extending second (122) channel portion, and wherein the channel portions are stacked above each other on a substrate. The method comprises forming a conductive line (130) extending beside and below the second channel portion, forming, on the conductive line, a first vertical interconnect structure (132) for electrically contacting the first channel portion, and thinning the substrate from the backside to expose the conductive line from below. The method further comprises forming a via hole (146) exposing the second channel portion from below, filling the via hole with a conductive material to form a second vertical interconnect structure (142), and forming a conductive structure (140) on the second vertical interconnect structure.

5. 发明授权

EP3496145B1 SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURED USING A PLASMA-PROCESSING STEP 有权
公开(公告)号：EP3496145B1
公开(公告)日：2020-09-23
申请号：EP17206476.8
申请日：2017-12-11
申请人： IMEC vzw
发明人： HIBLOT, Gaspard , VAN DER PLAS, Geert , VAN HUYLENBROECK, Stefaan
IPC分类号： H01L27/02

6. 发明公开

EP4391033A1 INTEGRATED CIRCUIT DEVICES COMPRISING BURIED POWER RAILS 审中-公开
公开(公告)号：EP4391033A1
公开(公告)日：2024-06-26
申请号：EP22216344.6
申请日：2022-12-23
申请人： Imec VZW
发明人： HIBLOT, Gaspard , CHAN, Boon Teik , MIRABELLI, Gioele
IPC分类号： H01L21/768 , H01L23/528 , H01L23/535 , H01L29/775
CPC分类号： H01L21/76897 , H01L23/5286 , H01L23/535 , H01L29/775 , H01L21/76831 , B82Y10/00 , H01L29/66439 , H01L29/0673 , H01L29/66545 , H01L29/42392 , H01L29/41725 , H01L27/088 , H01L21/823475 , H01L21/823481
摘要： Method for forming an integrated circuit device (98), comprising: a. forming (901) a semiconductor device on a frontside (11) of a substrate (1) comprising: a device layer (2) on the frontside (11) of the substrate (1), the device layer (2) comprising a first active device (20), the substrate (1) comprising: shallow trench isolation structures (139, 131, 132, 133), wherein adjacent shallow trench isolation structures (139, 131, 132, 133) are separated from each other by a separating portion (1391, 1312, 1323) comprising the substrate material (100), a via (130) filled with a sacrificial plug (4) extending through the substrate material (100) in a first separating portion (1312), and wherein the sacrificial plug (4) contacts a source or drain contact (21) of the first active device (20), b. removing (902) the substrate material (100) from a backside of the substrate (1), c. depositing (903) a liner (9) covering the backside (10) of the substrate (1), d. anisotropically etching (904) the liner (9) so as to expose a first end (41) of the sacrificial plug (4), while retaining at least part of the liner (9) in the separating portions (1391, 1312, 1323), e. removing (905) the sacrificial plug (4) selectively with respect to the liner (9), and f. providing (906) an electrically conductive material (30) in the via (130), electrically coupled to a buried power rail (31, 32).

7. 发明公开

EP3823031A1 BIPOLAR SELECTOR DEVICE FOR A MEMORY ARRAY 审中-公开
公开(公告)号：EP3823031A1
公开(公告)日：2021-05-19
申请号：EP19208600.7
申请日：2019-11-12
申请人： Imec VZW
发明人： HIBLOT, Gaspard , HOUSHMAND SHARIFI, Shamin , VAN DER PLAS, Geert
IPC分类号： H01L27/22 , H01L21/768 , H01L23/48 , H01L23/00 , H01L27/06
摘要： The present disclosure is related to the field of memory devices including memory arrays, in particular magnetic memory devices. The invention provides a method for fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices (11) in a semiconductor layer (12) of a first substrate, processing an interconnect layer (14) on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure (15) electrically connected to the plurality of selector devices, processing a plurality of memory elements (16) in an oxide layer (17) of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias (18) through the semiconductor layer to electrically connect the memory elements to the interconnect structure.

8. 发明公开

EP3819945A1 METHOD OF FORMING A VERTICAL CHANNEL DEVICE 审中-公开
公开(公告)号：EP3819945A1
公开(公告)日：2021-05-12
申请号：EP19207373.2
申请日：2019-11-06
申请人： Imec VZW
发明人： HIBLOT, Gaspard , BAUDOT, Sylvain
IPC分类号： H01L29/66 , H01L29/78
摘要： The present invention provides a method of forming a vertical channel transistor structure (1), comprising the steps of a) forming a bottom source/drain region (3a) on a substrate surface (2) and depositing a spacer oxide layer (13) over said bottom source/drain region (3a); b) forming vertically extending portions (5) and depositing gate material (4) on the deposited spacer oxide layer (13) such that the gate material is arranged over said bottom source/drain region (3a) and over said deposited spacer oxide layer (13) and wherein said vertically extending portions (5) are arranged around and are extending above said gate material (4); c) depositing spacer material (6) at sidewalls of said vertically extending portions (5), thereby defining a horizontal gap (7) between said vertically extending portions (5), said gap (7) being positioned vertically over said gate material (4) and said bottom source/drain portion (3a). The method further comprises the steps of d) forming a vertical opening (8) through said gate material (4) extending from said horizontal gap (7) down to said bottom source/drain region (3a); e) depositing an oxide (10) at the sidewalls of said gate material (4) in said vertical opening (8); and f) performing an epitaxial deposition process of a semiconductor material on said bottom source/drain portion (3a) to form a vertical channel structure (9) above said gate (4), wherein the width (w1) of the vertical channel structure (9) through said gate (4) is defined by the width of the horizontal gap (9) after said depositing of step e); g) planarizing the formed structure (1), thereby reducing the height of the vertical channel structure (9) and the deposited spacer material (6); and h) forming a top source/drain portion (3b) over the vertical channel structure (9).

9. 发明公开

EP3588239A1 LOW-TEMPERATURE VOLTAGE REFERENCE USING COULOMB BLOCKADE MECHANISM 有权
公开(公告)号：EP3588239A1
公开(公告)日：2020-01-01
申请号：EP18180932.8
申请日：2018-06-29
申请人： IMEC vzw
发明人： HIBLOT, Gaspard , PARVAIS, Bertrand
IPC分类号： G05F3/16 , B82Y10/00 , H01L29/76
摘要： The present disclosure provides a method of generating a reference voltage, including providing a first single-electron transistor (SET, 110) and a second SET (120) connected in series with the first SET, biasing the first SET and the second SET using a same biasing current (I b ), operating the first SET at a slope of a first Coulomb peak (210), wherein the slope of the first Coulomb peak is of a slope type selected from a rising slope (211r), a peak maximum (211m), and a falling slope (211f), operating the second SET at a slope of a second Coulomb peak (220) different from the first Coulomb peak, wherein the slope of the second Coulomb peak is of the same slope type as the slope of the first Coulomb peak, and generating the reference voltage (V ref ) based on a difference between a gate-to-source voltage (V gs1 ) of the first SET and a gate-to-source voltage (V gs2 ) of the second SET. A reference voltage generator (100) is also provided.

10. 发明公开

EP3567003A1 SELF-ALIGNED METHOD OF MAKING A TRANSISTOR WITH MULTIPLE NANOWIRE OR NANOSHEET CHANNELS, COMRPISING THE USE OF A SPACER COMPRISING EUV EXPOSED RESIST AS WELL AS NON-EXPOSED RESIST 审中-公开
公开(公告)号：EP3567003A1
公开(公告)日：2019-11-13
申请号：EP18171948.5
申请日：2018-05-11
申请人： IMEC vzw
发明人： HIBLOT, Gaspard , BAUDOT, Sylvain , MERTENS, Hans , JUSSOT, Julien
IPC分类号： B82Y10/00 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/06
摘要： A method (100) of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing (110) a wafer which comprises at least one fin of sacrificial layers (4) alternated with functional layers (3), and a dummy gate (1) covering a section of the fin between a first end (21) and a second end (22); at least partly removing (120) the sacrificial layers (4) at the first end (21) and the second end (22) thereby forming a void between the functional layers at the first and end (21, 22) such that the void is partly covered by the dummy gate; providing (130) resist material which oxidizes upon EUV exposure; exposing (140) the wafer to EUV light; selectively removing part of the unexposed resist (6) and removing (150) the dummy gate and the unexposed resist (5); forming (160) a gate between the functional layers and between the remaining parts of exposed resist (6) at the first end (21) and at the second end (22).

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