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    • 5. 发明公开
    • AUTOMATIC IIP2 CALIBRATION ARCHITECTURE
    • 自动IIP2校准架构
    • EP2111690A1
    • 2009-10-28
    • EP08706309.5
    • 2008-01-25
    • Icera Canada ULC
    • MANKU, TajinderBELLAOUAR, AbdellatifHOLDEN, Alan, R.SAFIRI, Hamid, R.
    • H04B1/26H04B17/00H04Q7/32
    • H04B1/12H03D2200/0045H04B17/21
    • An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.
    • 公开了一种用于无线收发器的集成式自动IIP2校准架构。 该架构使无线收发器能够以最少的附加电路产生具有二阶音调的测试射频(RF)信号。 特别地,使用本地收发器电路和测试适配器电路的组合来生成测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本地收发器功能的电路,其可用于生成测试(RF)信号。 测试适配器电路被添加到收发器芯片,更具体地添加到本地电路,以使本地电路能够在自测试操作模式下生成测试RF信号。 用于实现特定IIP2最小化方案的电路可以包含在收发器芯片上,用于在自检模式下进行自动IIP2校准。