专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP1496616B1 Teacher-pupil flip-flop 有权
标题翻译：师生触发器
公开(公告)号：EP1496616B1
公开(公告)日：2007-04-25
申请号：EP03256885.9
申请日：2003-10-30
申请人： IP-First LLC
发明人： Lundberg, James R
IPC分类号： H03K3/356
CPC分类号： H03K3/012 , G06F9/3869 , H03K3/356121

2. 发明公开

EP1496616A3 Teacher-pupil flip-flop 有权
标题翻译：师生触发器
公开(公告)号：EP1496616A3
公开(公告)日：2006-03-29
申请号：EP03256885.9
申请日：2003-10-30
申请人： IP-First LLC
发明人： Lundberg, James R
IPC分类号： H03K3/356
CPC分类号： H03K3/012 , G06F9/3869 , H03K3/356121
摘要： A teacher-pupil flip-flop with reduced register delay including a gate circuit (U1,U2), a stack circuit (711,713), a keeper circuit (705,707), a teacher output circuit, a latch circuit (709) and a pupil output circuit (710). The gate circuit switches after a setup delay in response to transitions of a clock signal. The stack circuit, coupled to the gate circuit output and to an input, switches an intermediate node pair to a preliminary state when the clock signal is low, and to a data state indicative of the input after the setup delay when the clock signal goes high. The keeper circuit maintains the data state and the teacher output circuit drives the output based on the data state while the clock is high. The latch circuit stores the data state and the pupil output circuit drives the output with valid data from the latch circuit after the clock signal goes low.

3. 发明公开

EP1496616A2 Teacher-pupil flip-flop 有权
标题翻译：莱勒 - 舒勒触发器
公开(公告)号：EP1496616A2
公开(公告)日：2005-01-12
申请号：EP03256885.9
申请日：2003-10-30
申请人： IP-First LLC
发明人： Lundberg, James R
IPC分类号： H03K3/356
CPC分类号： H03K3/012 , G06F9/3869 , H03K3/356121
摘要： A teacher-pupil flip-flop with reduced register delay including a gate circuit (U1,U2), a stack circuit (711,713), a keeper circuit (705,707), a teacher output circuit, a latch circuit (709) and a pupil output circuit (710). The gate circuit switches after a setup delay in response to transitions of a clock signal. The stack circuit, coupled to the gate circuit output and to an input, switches an intermediate node pair to a preliminary state when the clock signal is low, and to a data state indicative of the input after the setup delay when the clock signal goes high. The keeper circuit maintains the data state and the teacher output circuit drives the output based on the data state while the clock is high. The latch circuit stores the data state and the pupil output circuit drives the output with valid data from the latch circuit after the clock signal goes low.
摘要翻译：具有减小的寄存器延迟的教师 - 瞳孔触发器，包括门电路（U1，U2），堆叠电路（711,713），保持器电路（705,707），教师输出电路，锁存电路（709）和瞳孔输出电路（710）。响应于时钟信号的转换，门电路在建立延迟之后切换。当时钟信号为低电平时，耦合到门电路输出和输入的堆叠电路将中间节点对切换到初步状态，并且当时钟信号变高时，将其指示在建立延迟之后的输入。保持电路保持数据状态，教师输出电路在时钟为高电平时，基于数据状态驱动输出。锁存电路存储数据状态，瞳孔输出电路在时钟信号变为低电平后，从锁存电路驱动具有有效数据的输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式