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1. 发明授权

EP1189238B1 Method for erasing a flash EEPROM memory cell 失效
标题翻译：擦除快速EEPROM存储单元的方法
公开(公告)号：EP1189238B1
公开(公告)日：2006-05-24
申请号：EP01204255.2
申请日：1996-08-07
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
发明人： Van Houdt, Jan , Haspeslagh, Luc , Deferm, Ludo , Groeseneken, Guido , Maes, Herman
IPC分类号： G11C16/14 , G11C16/16
CPC分类号： G11C16/16 , G11C16/14

2. 发明授权

EP0762429B1 Method of programming a flash EEPROM memory cell optimized for low power consumption and a method for erasing said cell 失效
标题翻译：编程低功耗和擦除此单元的方法的一个快闪EEPROM存储单元的优化方法
公开(公告)号：EP0762429B1
公开(公告)日：2002-02-20
申请号：EP96870103.7
申请日：1996-08-07
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
发明人： Van Houdt, Jan , Haspeslagh, Luc , Deferm, Ludo , Groeseneken, Guido , Maes, Herman
IPC分类号： G11C16/06 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0425 , G11C5/142 , G11C16/10 , G11C16/16 , H01L27/115

3. 发明公开

EP0762429A2 Method of programming a flash EEPROM memory cell optimized for low power consumption and a method for erasing said cell 失效
标题翻译：编程低功耗和擦除此单元的方法的一个快闪EEPROM存储单元的优化方法
公开(公告)号：EP0762429A2
公开(公告)日：1997-03-12
申请号：EP96870103.7
申请日：1996-08-07
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
发明人： Van Houdt, Jan , Haspeslagh, Luc , Deferm, Ludo , Groeseneken, Guido , Maes, Herman
IPC分类号： G11C16/06 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0425 , G11C5/142 , G11C16/10 , G11C16/16 , H01L27/115
摘要： Fast 5V-only programming of a Flash EEPROM cell or array of such cells is disclosed. Use is made of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.
摘要翻译：几乎5V-只有快闪EEPROM细胞或细胞阵列的编程检查游离缺失盘。利用了增强型源极侧注入机制。这个概念需要，其用于电容性地耦合的高电压到浮动栅极上的场氧化物区的程序栅极。因此，一个非常高的注入电流编程过程中建立的。这种额外的编程栅，但是，显着提高了单元面积。本公开示出了非接触式5V-仅限Flash EEPROM阵列配置做，以便最小化面积开销上共享程序行凭借并通过该编程栅引起的。进一步，提出了一种存储器阵列具有共享字线这进一步增强了密度实现的。

4. 发明公开

EP1376676A2 Multibit non-volatile memory device and method 审中-公开
标题翻译： Multibit-Festwertspeicherbauelement und Verfahren
公开(公告)号：EP1376676A2
公开(公告)日：2004-01-02
申请号：EP03447166.4
申请日：2003-06-20
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , Infineon AG
发明人： Van Houdt, Jan , Haspeslagh, Luc
IPC分类号： H01L21/336 , H01L21/28 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , G11C16/0458 , H01L21/2815 , H01L21/28273 , H01L29/7887 , H01L29/7923
摘要： A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline.
Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.
摘要翻译：描述了具有第一导电类型的半导体衬底，第二导电类型的第一和第二结区的存储器，由此所述第一和第二结区分别是第一和第二位线的一部分。提供选择门，其是垂直于所述第一和所述第二位线的字线的一部分。每个单元的读，写和擦除功能仅使用两个多晶硅层，这简化了制造，每个存储单元具有至少两个用于存储表示至少一个位的电荷的位置。

5. 发明公开

EP0762429A3 Method of programming a flash EEPROM memory cell optimized for low power consumption and a method for erasing said cell 失效
标题翻译：编程低功耗和擦除此单元的方法的一个快闪EEPROM存储单元的优化方法
公开(公告)号：EP0762429A3
公开(公告)日：1999-01-27
申请号：EP96870103.7
申请日：1996-08-07
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
发明人： Van Houdt, Jan , Haspeslagh, Luc , Deferm, Ludo , Groeseneken, Guido , Maes, Herman
IPC分类号： G11C16/06 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0425 , G11C5/142 , G11C16/10 , G11C16/16 , H01L27/115
摘要： Fast 5V-only programming of a Flash EEPROM cell or array of such cells is disclosed. Use is made of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.

6. 发明公开

EP1376676A3 Multibit non-volatile memory device and method 审中-公开
标题翻译：多比特只读存储器装置和方法
公开(公告)号：EP1376676A3
公开(公告)日：2008-08-20
申请号：EP03447166.4
申请日：2003-06-20
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , Infineon AG
发明人： Van Houdt, Jan , Haspeslagh, Luc
IPC分类号： H01L21/336 , H01L21/28 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , G11C16/0458 , H01L21/2815 , H01L21/28273 , H01L29/7887 , H01L29/7923
摘要： A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline.
Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.

7. 发明公开

EP1189238A1 Method for erasing a flash EEPROM memory cell 失效
标题翻译： Verfahren zumLöscheneiner闪存EEPROM Speicherzelle
公开(公告)号：EP1189238A1
公开(公告)日：2002-03-20
申请号：EP01204255.2
申请日：1996-08-07
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
发明人： Van Houdt, Jan , Haspeslagh, Luc , Deferm, Ludo , Groeseneken, Guido , Maes, Herman
IPC分类号： G11C16/14 , G11C16/16
CPC分类号： G11C16/16 , G11C16/14
摘要： A method of erasing at least one nonvolatile memory cell is disclosed. The cell comprises : a semiconductor substrate including a source and a drain region and a channel therebetween; a floating gate extending over a portion of the drain region with a dielectric layer, therebetween and extending over a portion of said channel, further referred to as the floating gate channel; a control gate extending over another portion of the channel region, further referred to as the control-gate channel, and a program gate capacitively coupled through a further dielectric layer to said floating gate. The method comprises the steps of : applying a first negative voltage to said program gate; and applying a second voltage to at least one of said drain region and said substrate of said cell. The first negative voltage is in the order of -7V and is further substantially simultaneously applied to said control gate thereby coupling a negative voltage to said floating gate of said cell.
摘要翻译：公开了擦除至少一个非易失性存储单元的方法。电池包括：包括源极和漏极区域以及它们之间的沟道的半导体衬底; 一个浮置栅极，在漏极区域的一部分上延伸有介电层，并在该沟道的一部分上延伸，又称为浮动栅极沟道; 延伸到通道区域的另一部分上的控制栅极，进一步称为控制栅极通道，以及通过另一介质层电容耦合到所述浮动栅极的程序栅极。该方法包括以下步骤：向所述程序门施加第一负电压; 以及向所述电池的所述漏极区域和所述衬底中的至少一个施加第二电压。第一负电压是-7V的量级，并且进一步基本上同时施加到所述控制栅极，从而将负电压耦合到所述电池的所述浮动栅极。

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