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1. 发明公开

EP0746107A2 Programmable logic cell 失效
标题翻译： Programmierbares Logikelement
公开(公告)号：EP0746107A2
公开(公告)日：1996-12-04
申请号：EP96480067.6
申请日：1996-05-07
申请人： International Business Machines Corporation
发明人： Bertolet, Allan Robert , Clinton, Kim P.N. , Fuller, Christine Marie , Gould, Scott Whitney , Hartman, Steven Paul , Iadanza, Joseph Andrew , Keyser, Frank Ray , Millham, Eric Ernest , Reny, Timothy Shawn , Worth, Brian A. , Yasar, Gulson , Zittritsch, Terrance John
IPC分类号： H03K19/177
CPC分类号： H03K19/1737
摘要： A programmable logic cell (70) has four logic gates, two of which are configurable. The two configurable logic gates (88a,b) are positioned near the logic cell inputs. Each configurable logic gate (88a,b) has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates (90a,b) receive the outputs (100a,b) of the configurable logic gates (88a,b). Four independent logic cell input nodes (84a-d) are provided, each having associated therewith a programmable input multiplexer (78a-d). Each input multiplexer (78a-d) can have inputs connected to at least two types of interconnect conductors (L1-L4,72a,74a). The cell (70) also has two output paths, each having associated therewith an independently-controlled output multiplexer (98a,b). The output (116a,b) of each output multiplexer (98a,b) is connected to an input (104a,b) of the other output multiplexer (98a,b). Additional features include a multiplexer (96) having inputs (o,p) connected to two cell input nodes (84b,c), a select input (M) connected to a third logic cell input node (84a), and an output connected to a cell output node (116a); a system low-skew data (e.g., clock) input clock available to at least one of the input multiplexers (78a-d); a flip-flop (92) connected within the logic cell (70); and internal cell feedback (112). The preferred method of programming utilizes user-programmed SRAM memory cells (M1-M28; Fig.10).
摘要翻译：可编程逻辑单元（70）具有四个逻辑门，其中两个是可配置的。两个可配置逻辑门（88a，b）位于逻辑单元输入附近。每个可配置逻辑门（88a，b）具有两个输入，每个输入连接到四个逻辑单元输入中的一个。剩余的两个逻辑门（90a，b）接收可配置逻辑门（88a，b）的输出（100a，b）。提供了四个独立的逻辑单元输入节点（84a-d），每个具有与可编程输入多路复用器（78a-d）相关联的逻辑单元输入节点。每个输入多路复用器（78a-d）可以具有连接到至少两种类型的互连导体（L1-L4,72a，74a）的输入。单元（70）还具有两个输出路径，每个输出路径具有独立控制的输出多路复用器（98a，b）。每个输出多路复用器（98a，b）的输出（116a，b）连接到另一输出多路复用器（98a，b）的输入端（104a，b）。附加特征包括具有连接到两个单元输入节点（84b，c）的输入（o，p）的多路复用器（96），连接到第三逻辑单元输入节点（84a）的选择输入（M）单元输出节点（116a）; 用于至少一个输入多路复用器（78a-d）的系统低偏移数据（例如，时钟）输入时钟; 连接在逻辑单元（70）内的触发器（92）; 和内部单元反馈（112）。编程的首选方法利用用户编程的SRAM存储单元（M1-M28;图10）。

2. 发明公开

EP0746107A3 Programmable logic cell 失效
标题翻译：可编程逻辑单元
公开(公告)号：EP0746107A3
公开(公告)日：1996-12-11
申请号：EP96480067.6
申请日：1996-05-07
申请人： International Business Machines Corporation
发明人： Bertolet, Allan Robert , Clinton, Kim P.N. , Fuller, Christine Marie , Gould, Scott Whitney , Hartman, Steven Paul , Iadanza, Joseph Andrew , Keyser, Frank Ray , Millham, Eric Ernest , Reny, Timothy Shawn , Worth, Brian A. , Yasar, Gulson , Zittritsch, Terrance John
IPC分类号： H03K19/177
CPC分类号： H03K19/1737
摘要： A programmable logic cell (70) has four logic gates, two of which are configurable. The two configurable logic gates (88a,b) are positioned near the logic cell inputs. Each configurable logic gate (88a,b) has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates (90a,b) receive the outputs (100a,b) of the configurable logic gates (88a,b). Four independent logic cell input nodes (84a-d) are provided, each having associated therewith a programmable input multiplexer (78a-d). Each input multiplexer (78a-d) can have inputs connected to at least two types of interconnect conductors (L1-L4,72a,74a). The cell (70) also has two output paths, each having associated therewith an independently-controlled output multiplexer (98a,b). The output (116a,b) of each output multiplexer (98a,b) is connected to an input (104a,b) of the other output multiplexer (98a,b). Additional features include a multiplexer (96) having inputs (o,p) connected to two cell input nodes (84b,c), a select input (M) connected to a third logic cell input node (84a), and an output connected to a cell output node (116a); a system low-skew data (e.g., clock) input clock available to at least one of the input multiplexers (78a-d); a flip-flop (92) connected within the logic cell (70); and internal cell feedback (112). The preferred method of programming utilizes user-programmed SRAM memory cells (M1-M28; Fig.10).
摘要翻译：可编程逻辑单元（70）具有四个逻辑门，其中两个是可配置的。两个可配置逻辑门（88a，b）位于逻辑单元输入附近。每个可配置逻辑门（88a，b）具有两个输入，每个输入连接到四个逻辑单元输入中的一个。其余两个逻辑门（90a，b）接收可配置逻辑门（88a，b）的输出（100a，b）。提供了四个独立的逻辑单元输入节点（84a-d），每个节点具有与其相关联的可编程输入多路复用器（78a-d）。每个输入多路复用器（78a-d）可以具有连接到至少两种类型的互连导体（L1-L4,72a，74a）的输入。单元（70）还具有两个输出路径，每个输出路径具有与其相关联的独立控制的输出多路复用器（98a，98b）。每个输出多路复用器（98a，b）的输出（116a，b）连接到另一个输出多路复用器（98a，b）的输入（104a，b）。附加特征包括具有连接到两个单元输入节点（84b，c）的输入（o，p），连接到第三逻辑单元输入节点（84a）的选择输入（M）以及连接到一个单元输出节点（116a）; 对输入多路复用器（78a-d）中的至少一个可用的系统低偏移数据（例如，时钟）输入时钟; 连接在逻辑单元（70）内的触发器（92）; 和内部小区反馈（112）。编程的优选方法利用用户编程的SRAM存储单元（M1-M28;图10）。

3. 发明公开

EP0631149A1 Method and apparatus for testing of integrated circuit chips 失效
标题翻译： Verfahren und Apparat zum Testen von integrierte Schaltungchips。
公开(公告)号：EP0631149A1
公开(公告)日：1994-12-28
申请号：EP94107216.7
申请日：1994-05-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anschel, Morris , Ingraham, Anthony Paul , Lamb, Charles Robert , Lowell, Michael David , Markovich, Voya Rista , Mayr, Wolfgang , Murphy, Richard Gerald , Pierson, Mark Vincent , Powers, Tamar Alane , Reny, Timothy Shawn , Reynolds, Scott David
IPC分类号： G01R31/28
CPC分类号： G01R31/2863 , G01R31/2862 , G01R31/287 , G01R31/2877 , G01R31/2879 , G01R31/2886
摘要： A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.
摘要翻译：公开了半导体芯片的测试方法。单个半导体芯片具有I / O，电源和接地触点。在本发明的方法中，提供了一种芯片测试夹具系统。芯片测试夹具系统具有对应于半导体芯片上的触点的触点。载体触点具有树枝状表面。芯片触点与芯片测试夹具系统上的导体焊盘导电接触。测试信号输入矢量被施加到半导体芯片的输入，并从半导体芯片恢复输出信号矢量。测试后，将芯片从基板上取下。

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