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1. 发明公开

EP4152367A3 GLASS CORE WITH CAVITY STRUCTURE FOR HETEROGENEOUS PACKAGING ARCHITECTURE 审中-实审
公开(公告)号：EP4152367A3
公开(公告)日：2023-08-02
申请号：EP22189215.1
申请日：2022-08-08
申请人： INTEL Corporation
发明人： PAITAL, Sameer , LI, Yonggang , DARMAWIKARTA, Kristof Kuwawi , DUAN, Gang , PIETAMBARAM, Srinivas
IPC分类号： H01L21/60 , H01L25/065 , H01L23/15
摘要： A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.

2. 发明公开

EP4264667A1 MICROELECTRONIC STRUCTURES INCLUDING GLASS CORES 审中-实审
公开(公告)号：EP4264667A1
公开(公告)日：2023-10-25
申请号：EP21907382.2
申请日：2021-09-23
申请人： Intel Corporation
发明人： PIETAMBARAM, Srinivas V. , IBRAHIM, Tarek A. , DUAN, Gang , VADLAMANI, Sai , PENMECHA, Bharat Prasad
IPC分类号： H01L23/538 , H01L23/14

4. 发明公开

EP4156254A1 ELECTRONIC PACKAGING ARCHITECTURE WITH CUSTOMIZED VARIABLE METAL THICKNESS ON SAME BUILDUP LAYER 审中-实审
公开(公告)号：EP4156254A1
公开(公告)日：2023-03-29
申请号：EP22183759.4
申请日：2022-07-08
申请人： Intel Corporation
发明人： ECTON, Jeremy , DARMAWIKARTA, Kristof , NAD, Suddhasattwa , OJEDA, Oscar , NIE, Bai , MARIN, Brandon , DUAN, Gang , VEHONSKY, Jacob , OZKAN, Onur , HAEHN, Nicholas
IPC分类号： H01L23/498 , H01L23/538 , H01L21/48
摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

5. 发明公开

EP4152367A2 GLASS CORE WITH CAVITY STRUCTURE FOR HETEROGENEOUS PACKAGING ARCHITECTURE 审中-实审
公开(公告)号：EP4152367A2
公开(公告)日：2023-03-22
申请号：EP22189215.1
申请日：2022-08-08
申请人： INTEL Corporation
发明人： PAITAL, Sameer , LI, Yonggang , DARMAWIKARTA, Kristof Kuwawi , DUAN, Gang , PIETAMBARAM, Srinivas
IPC分类号： H01L21/60 , H01L25/065 , H01L23/15
摘要： A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.

6. 发明公开

EP4027378A2 POROUS FIRST LEVEL INTERCONNECT (FLI) BUMPS FOR REDUCING BUMP THICKNESS VARIATION SENSITIVITY TO ENABLE BUMP PITCH SCALING 审中-公开
公开(公告)号：EP4027378A2
公开(公告)日：2022-07-13
申请号：EP21196781.5
申请日：2021-09-15
申请人： INTEL Corporation
发明人： AHMED, Numair , LEE, Kyu Oh , MARIN, Brandon , DUAN, Gang
IPC分类号： H01L23/00
摘要： Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.

7. 发明公开

EP3961701A1 CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS 审中-公开
公开(公告)号：EP3961701A1
公开(公告)日：2022-03-02
申请号：EP21198092.5
申请日：2020-02-10
申请人： INTEL Corporation
发明人： PIETAMBARAM, Srinivas V. , DUAN, Gang , KULKARNI, Deepak , MANEPALLI, Rahul N. , GUO, Xiaoying
IPC分类号： H01L23/538
摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages.

8. 发明公开

EP4386827A1 LOW Z-HEIGHT, GLASS-REINFORCED PACKAGE WITH EMBEDDED BRIDGE 审中-公开
公开(公告)号：EP4386827A1
公开(公告)日：2024-06-19
申请号：EP23199562.2
申请日：2023-09-25
申请人： INTEL Corporation
发明人： DUAN, Gang , MANEPALLI, Rahul , PIETAMBARAM, Srinivas , MARIN, Brandon , NAD, Suddhasattwa , ECTON, Jeremy
IPC分类号： H01L23/00 , H01L25/065 , H01L25/00
CPC分类号： H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L24/16 , H01L24/17
摘要： An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

9. 发明公开

EP4220694A2 FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH 审中-实审
公开(公告)号：EP4220694A2
公开(公告)日：2023-08-02
申请号：EP23158294.1
申请日：2018-01-12
申请人： INTEL Corporation
发明人： LIU, Changhua , GUO, Xiaoying , ALEKSOV, Aleksandar , CHO, Steve S. , ARANA, Leonel , MAY, Robert , DUAN, Gang
IPC分类号： H01L21/60 , H01L23/498 , H01L21/48 , H01L25/065 , H01L23/538 , H01L21/683 , H01L25/18
摘要： A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. Forming a first solder resist (SR) layer on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. Forming a second solder resist (SR) layer on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

10. 发明公开

EP4184569A2 MICROELECTRONIC PACKAGES WITH REGULAR SOLDER JOINTS AND NO-REMELT, FULL INTERMETALLIC COMPOUND JOINTS BETWEEN TWO SUBSTRATES 审中-实审
公开(公告)号：EP4184569A2
公开(公告)日：2023-05-24
申请号：EP22201685.9
申请日：2022-10-14
申请人： INTEL Corporation
发明人： SHAN, Bohan , CHEN, Haobo , KARHADE, Omkar , SANKARASUBRAMANIAN, Malavarayan , XU, Dingying , DUAN, Gang , NIE, Bai , GUO, Xiaoying , DARMAWIKARTA, Kristof , FENG, Hongxia , PIETAMBARAM, Srinivas V. , ECTON, Jeremy
IPC分类号： H01L23/485 , H01L21/603 , H01L25/065 , H05K3/34
摘要： In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

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