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1. 发明公开

EP1983552A1 Semiconductor production system 审中-公开
标题翻译：产品编号：
公开(公告)号：EP1983552A1
公开(公告)日：2008-10-22
申请号：EP08012855.6
申请日：2001-08-20
申请人： Hitachi Ltd.
发明人： Naya, Hidemitsu , Tomiyoshi, Rikio , Moriyama, Shigeo , Kikuchi, Mutsumi , Shimamura, Kotaro
IPC分类号： H01L21/00
CPC分类号： H01L21/67225 , G03F7/70508 , G03F7/70991 , G05B19/418 , G05B19/41855 , G05B2219/31323 , G05B2219/31326 , G05B2219/45031 , H01L21/67276 , H04L67/1097 , Y02P90/185 , Y02P90/24 , Y02P90/265
摘要： A semiconductor production system has a semiconductor manufacturing apparatus (20) having an exposure unit, a control unit for controlling the exposure unit and a storage device; a semiconductor inspection apparatus (10) having an observation unit, a control unit for controlling the observation unit and a storage device; and a storage device (30) commonly used by the semiconductor manufacturing apparatus and the semiconductor inspection apparatus. The manufacturing apparatus (20), the inspection apparatus (10) and the commonly used storage device (30) are interconnected via a storage area network (40). With the semiconductor manufacturing apparatus and the storage device linked together via the storage area network, a large volume of image data or design data can be communicated at high speed, thus improving the system throughput.
摘要翻译：半导体制造系统具有具有曝光单元的半导体制造装置（20），用于控制曝光单元的控制单元和存储装置; 具有观察单元的半导体检查装置（10），用于控制观察单元的控制单元和存储装置; 以及半导体制造装置和半导体检查装置共同使用的存储装置（30）。制造装置（20），检查装置（10）和常用的存储装置（30）经由存储区域网络40互连。随着半导体制造装置和存储装置经由存储区域网络连接在一起，可以高速地传送大量图像数据或设计数据，从而提高系统吞吐量。

2. 发明公开

EP1256879A3 Data processor having cache memory 失效
标题翻译：数据处理器缓存
公开(公告)号：EP1256879A3
公开(公告)日：2005-02-09
申请号：EP02014525.6
申请日：1994-08-03
申请人： Hitachi, Ltd.
发明人： Hotta, Takashi , Kurihara, Toshihiko , Tanaka, Shigeya , Sawamoto, Hideo , Osumi, Akiyoshi , Saito, Koji , Shimamura, Kotaro
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).

3. 发明公开

EP1530106A8 Electronic controller 审中-公开
标题翻译：电子控制单元
公开(公告)号：EP1530106A8
公开(公告)日：2006-02-01
申请号：EP04026206.5
申请日：2004-11-04
申请人： Hitachi, Ltd.
发明人： Morita, Yuichiro , Shimamura, Kotaro , Tsunedomi, Kunihiko , Imura, Shinya , Sasaki, Shoji , Yokoyama, Takanori
IPC分类号： G05B19/042
CPC分类号： G05B19/0423
摘要： The present invention relates to an electronic controller including an input means (4) for fetching an external signal and performing an input process such as A-D conversion, an operation means (2), upon receipt of processing results of the input means (4), for executing operations according to a predetermined program, an output means (6) for performing the output process for a signal to the outside on the basis of the operation results of the operation means (2), and a timer means (5) for outputting at least two of an input process start signal for starting the input process by the input means (4), an output process start signal for starting the output process by the output means (6), and an operation start signal for starting the operation by the operation means (2).

4. 发明授权

EP0866389B1 Replicated controller and fault recovery method thereof 失效
标题翻译：复制控制器和纠错方法及其
公开(公告)号：EP0866389B1
公开(公告)日：2002-06-12
申请号：EP98301664.3
申请日：1998-03-06
申请人： Hitachi, Ltd.
发明人： Shimamura, Kotaro , Morita, Yuuichiro , Takahashi, Yoshitaka , Hotta, Takashi , Satou, Hiroyasu , Ueda, Shigeta , Bando, Akira , Suzuki, Hirokazu , Sakamoto, Koji
IPC分类号： G05B9/03 , G06F11/18
CPC分类号： G06F11/182 , G05B9/03 , G06F11/184 , G06F11/188 , Y10S707/99953
摘要： A replicated controller and a fault recovery method therefor which can restore a faulty system to a normal state without interrupting operation of an equipment, even in an equipment controller performing processing with short operating periods. In a fault recovery method for a replicated controller, control data is divided into a plurality of blocks on the basis of dependency of the blocks, and a plurality of blocks are transferred in a sequential order of superiority of the dependency from the normally operating system to the faulty system in a period over a plurality of operating periods. BY this, even in an equipment controller performing processing at a short operating period, the system, in which failure is caused, can be restored into normal state without interrupting operation of the equipment.

5. 发明公开

EP2709015A3 Logic circuit and control apparatus using the same 失效
标题翻译：逻辑电路和控制装置，从而
公开(公告)号：EP2709015A3
公开(公告)日：2016-09-21
申请号：EP13182000.3
申请日：2013-08-28
申请人： Hitachi, Ltd.
发明人： Kanekawa, Nobuyasu , Katsuta, Keiichi , Sakata, Teruaki , Ikeda, Naohiro , Kurihara, Naoki , Shimamura, Kotaro
IPC分类号： G06F11/263 , G06F11/22
CPC分类号： G06F11/263 , G06F11/2215
摘要： Test pattern injecting means are synchronized not by providing a common operation clock thereto but by synchronizing them to the output timing of function blocks. By synchronizing the test pattern injecting means to the output timing of the function blocks, which has a longer cycle than the operation clock, the effect of the variation in signal delay (skew) can be reduced.

6. 发明公开

EP2177413A3 Vehicle control system 有权
标题翻译： Fahrzeugsteuerungssystem
公开(公告)号：EP2177413A3
公开(公告)日：2011-02-16
申请号：EP10150630.1
申请日：2005-03-31
申请人： Hitachi Ltd.
发明人： Yoshimura, Kentaro , Sakurai, Kohei , Kanekawa, Nobuyasu , Morita, Yuichiro , Takahashi, Yoshiaki , Kurosawa, Kenichi , Minowa, Toshimichi , Hoshino, Masatoshi , Nakatsuka, Yasuhiro , Shimamura, Kotaro , Tsunedomi, Kunihiko , Sasaki, Shoji
IPC分类号： B60W10/20 , B60W10/18 , B60W10/04 , B60W50/02 , B60W50/04
CPC分类号： B60W30/00 , B60K6/46 , B60K6/52 , B60L3/0023 , B60L3/003 , B60L3/0076 , B60L3/0092 , B60L15/2009 , B60L2240/12 , B60L2240/20 , B60L2240/24 , B60L2240/423 , B60L2250/26 , B60T7/12 , B60W10/04 , B60W10/06 , B60W10/08 , B60W10/10 , B60W10/18 , B60W10/20 , B60W20/00 , B60W40/08 , B60W40/10 , B60W50/02 , B60W50/0225 , B60W50/04 , B60W2510/20 , B60W2510/202 , B60W2520/14 , B60W2540/10 , B60W2540/12 , B60W2550/20 , B62D5/046 , B62D5/0481 , B62D6/00 , G06F11/0796 , Y02T10/6217 , Y02T10/6265 , Y02T10/6286 , Y02T10/645 , Y02T10/72 , Y02T10/7275 , Y02T90/16
摘要： A vehicle control system comprising a plurality of actuator driving means (300) for controlling actuators (400) in accordance with a driver's demand and a vehicle status, and communication means for interconnecting said plurality of actuator driving means (300), thereby controlling at least one of driving, steering and braking of a vehicle (50), wherein each of said actuator driving means (300) has control method selecting means (220) for selecting an actuator control method based on an operation state of itself and operation states of the other actuator driving means (300).
摘要翻译：一种车辆控制系统，包括：传感器控制器（2），用于接收指示车辆（50）的状态变量的传感器信号和从驾驶员施加的操作量;命令控制器（1），用于基于所述控制目标值生成控制目标值由传感器控制器（2）吸入的传感器信号和用于从命令控制器（1）接收控制目标值并操作致动器（5）以控制车辆（50）的致动器控制器（3），那三个控制器通过网络（N1）互连。执行器控制器（3）包括控制目标值生成单元（3B），用于基于由传感器控制器（2）接收并由致动器控制器（3）经由网络（N1）接收的传感器信号来产生控制目标值）当由指令控制器（1）产生的控制目标值异常时，根据由控制目标值生成单元（3B）产生的控制目标值来控制致动器（5）。

7. 发明授权

EP1983551B1 Semiconductor inspection system 有权
标题翻译：检测系统半导体
公开(公告)号：EP1983551B1
公开(公告)日：2010-10-20
申请号：EP08012854.9
申请日：2001-08-20
申请人： Hitachi Ltd.
发明人： Naya, Hidemitsu , Tomiyoshi, Rikio , Moriyama, Shigeo , Kikuchi, Mutsumi , Shimamura, Kotaro
IPC分类号： H01L21/00
CPC分类号： H01L21/67225 , G03F7/70508 , G03F7/70991 , G05B19/418 , G05B19/41855 , G05B2219/31323 , G05B2219/31326 , G05B2219/45031 , H01L21/67276 , H04L67/1097 , Y02P90/185 , Y02P90/24 , Y02P90/265

8. 发明授权

EP0637800B1 Data processor having cache memory 失效
标题翻译：数据处理器缓存
公开(公告)号：EP0637800B1
公开(公告)日：2003-02-19
申请号：EP94305771.1
申请日：1994-08-03
申请人： Hitachi, Ltd.
发明人： Hotta, Takashi , Kurihara, Toshihiko , Tanaka, Shigeya , Sawamoto, Hideo , Osumi, Akiyoshi , Saito, Koji , Shimamura, Kotaro
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028

9. 发明公开

EP1256879A2 Data processor having cache memory 失效
标题翻译： Datenprozessor mit Cache-Speicher
公开(公告)号：EP1256879A2
公开(公告)日：2002-11-13
申请号：EP02014525.6
申请日：1994-08-03
申请人： Hitachi, Ltd.
发明人： Hotta, Takashi , Kurihara, Toshihiko , Tanaka, Shigeya , Sawamoto, Hideo , Osumi, Akiyoshi , Saito, Koji , Shimamura, Kotaro
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A data processor has a main memory (203) which stores data and instructions to be used by the processor, an instruction processor (201) and two cache memories (100,101). The first cache memory (101) is a large capacity port direct mapped cache memory, and the second cache memory (100) is a small capacity two port set associative cache memory. The instruction processor (201) controls the transfer of data to/from the cache memories (100,102) on the basis of instruction from the main memory, so that data needed frequently is stored in the first cache memory (101) and data needed less frequently is stored in the second cache memory (100). With such an arrangement, data stored in the second cache memory (100) can be removed therefrom after it has been accessed, and other data stored therein, thereby increasing the probability that data needed at any time will be in the first or second cache memories (101,100), without storing useless data on the first cache memory (101).
摘要翻译：数据处理器具有存储由处理器使用的数据和指令的主存储器（203），指令处理器（201）和两个高速缓存存储器（100,101）。第一高速缓冲存储器（101）是大容量端口直接映射高速缓存存储器，第二高速缓存存储器（100）是小容量二端口组关联高速缓冲存储器。指令处理器（201）根据来自主存储器的指令来控制向高速缓冲存储器（100,102）传输数据，从而频繁地存储所需的数据存储在第一高速缓冲存储器（101）中，并且数据需要较少存储在第二高速缓冲存储器（100）中。通过这样的布置，存储在第二高速缓冲存储器（100）中的数据可以在其被访问之后被移除，并且存储在其中的其他数据，从而增加在任何时间所需的数据将在第一或第二高速缓冲存储器（101,100），而不在第一高速缓存存储器（101）上存储无用的数据。

10. 发明授权

EP2709015B1 Logic circuit and control apparatus using the same 失效
公开(公告)号：EP2709015B1
公开(公告)日：2019-08-21
申请号：EP13182000.3
申请日：2013-08-28
申请人： Hitachi, Ltd.
发明人： Kanekawa, Nobuyasu , Katsuta, Keiichi , Sakata, Teruaki , Ikeda, Naohiro , Kurihara, Naoki , Shimamura, Kotaro
IPC分类号： G06F11/263 , G06F11/22

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