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1. 发明授权

EP0539830B1 Pseudo-NMOS fine/coarse wired-or tapped delay line 失效
标题翻译：伪NMOS粗略/精细硬连线或设置有抽头延迟线
公开(公告)号：EP0539830B1
公开(公告)日：1998-05-27
申请号：EP92117847.1
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr.
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13 , H03K5/14 , H03K17/693
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747

2. 发明公开

EP0792019A1 A wired-or multiplexer device 失效
标题翻译： Verdrahteter Oder多路复用器
公开(公告)号：EP0792019A1
公开(公告)日：1997-08-27
申请号：EP97104612.3
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr.
IPC分类号： H03K17/00
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A wired-or multiplexer (MUX) device (215) for selecting or not selecting an input signal comprises a first and a second pseudo-NMOS inverter (822/802 and 897/882), a node (842) comprised of a connection between a data output of the first inverter and a data input of the second inverter, an adjustable control voltage (112) for applying a biasing voltage to the first and second control inputs of the first and a second pseudo-NMOS inverters to thereby control the amount of charge supplied to the node and the data output of the second pseudo-MOS inverter; and a select circuit connected to the node for permitting or not permitting the input signal to propagate to the data output of the second pseudo-MOS inverter.
摘要翻译：用于选择或不选择输入信号的有线或多路复用器（MUX）设备（215）包括第一和第二伪NMOS反相器（822/802和897/882），节点（842）包括：第一反相器的数据输出和第二反相器的数据输入，用于向第一和第二伪NMOS反相器的第一和第二控制输入施加偏置电压的可调节控制电压（112），从而控制量提供给节点的电荷和第二伪MOS反相器的数据输出; 以及连接到节点的选择电路，用于允许或不允许输入信号传播到第二伪MOS反相器的数据输出。

3. 发明公开

EP0539832A3 CMOS pseudo-NMOS programmable capacitance time vernier system and method for controlled delay of timing edges 失效
标题翻译： CMOS伪NMOS可编程电容时间游标系统和用于时间边缘受控延迟的方法
公开(公告)号：EP0539832A3
公开(公告)日：1995-04-19
申请号：EP92117854.7
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr.
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747
摘要： An integrated circuit system having integrated thereon, one or more time vernier subsystems (106,108,110) for fine tuning coarse timing edges of corresponding input signals (103). The system comprises means for generating a control signal for each input signal (103) to specify the amount of fine tuning, and at least one time vernier subsystem having a first input to receive the control signal (112) and a second input to receive a corresponding input signal (103), and means for fine tuning the coarse edges of the corresponding input signal according to the specified amount of fine tuning and for outputting the result.
摘要翻译：一种集成电路系统，其上集成有一个或多个时间游标子系统（106,108,110），用于微调相应输入信号（103）的粗略定时边沿。该系统包括用于产生用于每个输入信号（103）的控制信号以指定微调量的装置，以及至少一个游标子系统，该至少一个游标子系统具有接收控制信号（112）的第一输入和接收相应的输入信号（103），以及根据指定的微调量对相应输入信号的粗边进行微调并输出结果的装置。

4. 发明公开

EP0539830A3 Pseudo-NMOS fine/coarse wired-or tapped delay line 失效
标题翻译：伪NMOS细/粗线或抽头延迟线
公开(公告)号：EP0539830A3
公开(公告)日：1995-08-09
申请号：EP92117847.1
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr.
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13 , H03K5/14 , H03K17/693
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747
摘要： The present invention is directed to a delay line (206) for providing fine timing adjustment on subsequent edges of an input signal (203). The delay line (206) comprises a plurality of delay elements (F₁, ... F n , C₁ ... C n ) for fine tuning the position in time of the timing edges of the input signal (203). Each delay element has a data input and data output where the data output is connected to the subsequent delay element's data input, thereby forming a delay line with delay elements connected in series. This implementation facilitates the addition of fine increments of delay to be added to the input signal and thereby enable fine tuning of timing edges. Also, included is a wired-OR multiplexer (215) having data inputs connected to the data outputs of the plurality of the delay elements (F₁, ... F n , C₁ ... C n ) and a control input to select a particular data output to thereby provide an output signal (204) having delayed timing edges.
摘要翻译：本发明涉及用于在输入信号（203）的后续边缘上提供精确定时调整的延迟线（206）。延迟线（206）包括多个延迟元件（F 1，... F n，C 1 ... C n），用于微调输入信号（203）的定时边缘的时间位置。每个延迟元件具有数据输入和数据输出，其中数据输出连接到后续延迟元件的数据输入，从而形成具有串联连接的延迟元件的延迟线。这种实施方式有助于增加延迟的细微增量以添加到输入信号，从而使得能够微调定时边缘。还包括一个线或逻辑多路复用器（215），它具有与多个延迟元件（F 1，... F n，C 1 ... C n）的数据输出端相连的数据输入端和一个用于选择特定数据输出，从而提供具有延迟的定时边缘的输出信号（204）。

5. 发明公开

EP0539831A2 Pseudo-NMOS programmable capacitance delay element 失效
标题翻译：伪NMOS-Technik中的程序设计者Kapazitätsverzögerungselement。
公开(公告)号：EP0539831A2
公开(公告)日：1993-05-05
申请号：EP92117853.9
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr. , Pumphrey, Edward Gary
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13 , H03K5/14
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A delay element (210) for fine tuning the position in time of timing edges of an input signal (203), comprising a first and a second inventer (307, 314), each comprising a data input, a control input and a data output. The delay element (210) further comprises a node (310) comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage (112) is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node (310). Finally, the variable capacitance means (308) is connected to the node (310) for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal (203) propagating from the first inverter (307) to the second inverter (314).
摘要翻译：一种用于在输入信号（203）的定时边缘的时间内微调位置的延迟元件（210），包括第一和第二发明人（307,314），每个包括数据输入，控制输入和数据输出。延迟元件（210）还包括由第一反相器的数据输出与第二反相器的数据输入之间的连接构成的节点（310）。包括可调控制电压（112），用于向第一和第二控制输入施加偏置电压，从而控制提供给节点（310）的电荷量。最后，可变电容装置（308）连接到节点（310），用于向节点施加有限量的电容以延迟，从而在时间上微调从第一反相器（...）传播的输入信号（203）的定时边缘 307）连接到第二逆变器（314）。

6. 发明公开

EP0539828A2 Variable width current mirror digital-to-analog converter (DAC) system and method for generating a control voltage for delay generation 失效
标题翻译：可变宽度电流镜的数字/模拟用于产生控制电压，以延迟生成系统和方法。
公开(公告)号：EP0539828A2
公开(公告)日：1993-05-05
申请号：EP92117841.4
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr. , Barnes, James Oliver , Hulings, James R.
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A current mirror digital to analog converter (104) for generating an analog output signal from a digital input (432), comprising a first field effect transistor (410) having a gate, source, and drain electrode, a current source (412) for supplying a constant reference current, having a first node (408) connected to the first gate and the first drain electrodes and having a second node connected to ground. A variable width field effect transistor array (414, 416, 418, 420, 422, 430) is connected to the first node (408) of the current source for enabling small voltage adjustments to be made to the first node based on the digital input signal, wherein the voltage at the node represents the analog voltage signal output.
摘要翻译：电流镜数字到模拟转换器（104），用于在模拟输出信号从包括具有栅极，源极的第一场效应晶体管（410）的数字输入端（432）产生，和漏极电极，电流源（412），用于提供恒定参考电流，具有连接到所述第一栅极和第一漏极电极的第一节点（408）并具有连接到地的第二个节点。可变宽度的场效应晶体管阵列（414，416，418，420，422，430）连接到所述电流源的所述第一节点（408），用于使小电压调整基于所述数字输入第一节点，以便进行信号，在darstellt的模拟电压信号输出的节点worin的电压。

7. 发明授权

EP0539831B1 Pseudo-NMOS programmable capacitance delay element 失效
标题翻译：在伪NMOS技术可编程延迟元件容量
公开(公告)号：EP0539831B1
公开(公告)日：1998-06-03
申请号：EP92117853.9
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr. , Pumphrey, Edward Gary
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13 , H03K5/14
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747

8. 发明公开

EP0539828A3 Variable width current mirror digital-to-analog converter (DAC) system and method for generating a control voltage for delay generation 失效
标题翻译：可变宽度电流镜像数字 - 模拟转换器（DAC）系统以及用于产生用于延迟产生的控制电压的方法
公开(公告)号：EP0539828A3
公开(公告)日：1995-08-09
申请号：EP92117841.4
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr. , Barnes, James Oliver , Hulings, James R.
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A current mirror digital to analog converter (104) for generating an analog output signal from a digital input (432), comprising a first field effect transistor (410) having a gate, source, and drain electrode, a current source (412) for supplying a constant reference current, having a first node (408) connected to the first gate and the first drain electrodes and having a second node connected to ground. A variable width field effect transistor array (414, 416, 418, 420, 422, 430) is connected to the first node (408) of the current source for enabling small voltage adjustments to be made to the first node based on the digital input signal, wherein the voltage at the node represents the analog voltage signal output.
摘要翻译：一种用于从数字输入（432）产生模拟输出信号的电流镜像数模转换器（104），包括具有栅极，源极和漏极的第一场效应晶体管（410），电流源（412）提供恒定参考电流，具有连接到第一栅极和第一漏极电极的第一节点（408），并具有连接到地的第二节点。可变宽度场效应晶体管阵列（414,416,418,420,422,430）连接到电流源的第一节点（408），用于基于数字输入对第一节点进行小的电压调整信号，其中节点处的电压表示模拟电压信号输出。

9. 发明公开

EP0539832A2 CMOS pseudo-NMOS programmable capacitance time vernier system and method for controlled delay of timing edges 失效
标题翻译： CMOS伪NMOS可编程电容Zeitvernierssystem和方法用于定时的边缘的控制延迟。
公开(公告)号：EP0539832A2
公开(公告)日：1993-05-05
申请号：EP92117854.7
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr.
IPC分类号： H03M1/66 , G01R31/28 , H03K5/13
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747
摘要： An integrated circuit system having integrated thereon, one or more time vernier subsystems (106,108,110) for fine tuning coarse timing edges of corresponding input signals (103). The system comprises means for generating a control signal for each input signal (103) to specify the amount of fine tuning, and at least one time vernier subsystem having a first input to receive the control signal (112) and a second input to receive a corresponding input signal (103), and means for fine tuning the coarse edges of the corresponding input signal according to the specified amount of fine tuning and for outputting the result.
摘要翻译：一种集成电路系统，其具有集成在其中，一个或多个时间游标子系统（106108110），用于微调粗定时相应的输入信号（103）的边缘。该系统包括用于产生对各输入信号（103），以指定微调的量的控制信号，以及具有一个第一输入端的至少一个时间游标子系统以接收所述控制信号（112）和一个第二输入，用于接收相应的输入信号（103）的装置，以及用于微调CORRESPONDINGgemäß到指定的微调的量和用于输出铃声的结果的输入信号的粗边缘。

10. 发明授权

EP0792019B1 A wired-or multiplexer device 失效
标题翻译：有线或多路复用器
公开(公告)号：EP0792019B1
公开(公告)日：2000-12-20
申请号：EP97104612.3
申请日：1992-10-19
申请人： Hewlett-Packard Company
发明人： Koerner, Christopher , Gutierrez, Albert, Jr.
IPC分类号： H03K17/00
CPC分类号： G01R31/2841 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00097 , H03M1/687 , H03M1/745 , H03M1/747

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