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1. 发明授权

EP0658858B1 Graphics computer 失效
标题翻译：图形计算机系统
公开(公告)号：EP0658858B1
公开(公告)日：2002-03-13
申请号：EP94309123.1
申请日：1994-12-07
申请人： Hitachi, Ltd.
发明人： Ohba, Mamoru , Watanabe, Mitsuru , Minami, Rika , Katsura, Koyo
IPC分类号： G06T11/20 , G06T1/60
CPC分类号： G06T11/203

2. 发明公开

EP0658858A3 Graphics computer 失效
标题翻译：图形计算机系统。
公开(公告)号：EP0658858A3
公开(公告)日：1996-07-24
申请号：EP94309123.1
申请日：1994-12-07
申请人： HITACHI, LTD.
发明人： Ohba, Mamoru , Watanabe, Mitsuru , Minami, Rika , Katsura, Koyo
IPC分类号： G06T11/20 , G06T1/60
CPC分类号： G06T11/203
摘要： To reduce the hardware of the graphics computer in size and reduce the cost of the hardware by uniting the frame buffer and the main memory into one to process graphics data in the CPU. The frame buffer is arranged in the main memory, and a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer are provided for the said graphics computer. Especially, the said memories are formed so that the single function procedure and the multifunction procedure can be selected to suit the drawing object in them. In addition, the single function procedure includes the line drawing procedure that uses data tables and the multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one, the CPU has come to process graphics data. Thus, the graphics computer hardware has been reduced in size and the cost of the hardware has been reduced.

3. 发明公开

EP0476478A3 Digital pulse processing device 失效
标题翻译：数字脉冲处理装置
公开(公告)号：EP0476478A3
公开(公告)日：1992-07-15
申请号：EP91115226.2
申请日：1991-09-09
申请人： HITACHI, LTD.
发明人： Ohba, Mamoru , Watabe, Mitsuru , Minami, Rika , Obara, Sanshiro
IPC分类号： G01P3/489
CPC分类号： G01P3/489
摘要： A digital pulse processing device is capable of selecting precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters 110 and 111 that can be separated from and coupled with each other, a mode control circuit 129 for instructing separation and coupling of the counters 110 and 111, and a control circuit 116 for separating and coupling the counters 110 and 111 in accordance with the instruction of the mode control circuit 129. An overflow condition of the timer 119 is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow. A register 128 is provided to hold the value of the timer 119 when a microcomputer reads in the counter 111. In this way, even when ΔA(i) = 0, speed detection operation can be executed using the value of the counter 111 obtained synchronously with the counting of the counter 110.

4. 发明公开

EP0371443A3 A saving and restoring method and a processor system for implementation of the same method 失效
标题翻译：节省和恢复方法和用于实现相同方法的处理器系统
公开(公告)号：EP0371443A3
公开(公告)日：1992-02-12
申请号：EP89121903.2
申请日：1989-11-28
申请人： HITACHI, LTD.
发明人： Ohba, Mamoru , Morinaga, Shigeki , Watabe. Mitsuru , Kida, Hiroyuki
IPC分类号： G06F9/46
CPC分类号： G06F9/461 , G06F9/30025 , G06F9/3861 , G06F9/3885
摘要： In a coprocessor system having a central processing unit (CPU, 100) as a host processor, a floating-point processing unit (FPU, 101) as a coprocessor and a memory (RAM, 103), coupled with each other through buses (104-106), when the CPU issues a save command to the FPU (101), the FPU (101) discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU (101) upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU (101) interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU (101) executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefore.

5. 发明公开

EP0658858A2 Graphics computer 失效
标题翻译： Graphisches Rechnersystem。
公开(公告)号：EP0658858A2
公开(公告)日：1995-06-21
申请号：EP94309123.1
申请日：1994-12-07
申请人： HITACHI, LTD.
发明人： Ohba, Mamoru , Watanabe, Mitsuru , Minami, Rika , Katsura, Koyo
IPC分类号： G06T11/20 , G06T1/60
CPC分类号： G06T11/203
摘要： To reduce the hardware of the graphics computer in size and reduce the cost of the hardware by uniting the frame buffer and the main memory into one to process graphics data in the CPU. The frame buffer is arranged in the main memory, and a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer are provided for the said graphics computer. Especially, the said memories are formed so that the single function procedure and the multifunction procedure can be selected to suit the drawing object in them. In addition, the single function procedure includes the line drawing procedure that uses data tables and the multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one, the CPU has come to process graphics data. Thus, the graphics computer hardware has been reduced in size and the cost of the hardware has been reduced.
摘要翻译：通过将帧缓冲区和主存储器整合为一个来处理CPU中的图形数据来减小图形计算机的硬件尺寸并降低硬件成本。帧缓冲器被布置在主存储器中，并且DMAC用于从用于显示的帧缓冲器中读取像素数据，用于接收像素数据并将其显示在诸如LCD等的显示装置上的显示器和存储器用于存储CPU用于绘制所述帧缓冲器中的像素数据的程序用于所述图形计算机。特别地，所述存储器被形成为使得可以选择单个功能过程和多功能过程以适合它们中的绘制对象。此外，单个功能过程包括使用数据表的线条图和使用模式表和掩码表的多值扩展过程。由于帧缓冲器和主存储器被组合成一个，所以CPU已经处理图形数据。因此，图形计算机硬件的尺寸已经减小，并且硬件的成本已经降低。

6. 发明授权

EP0287115B1 Coprocessor and method of controlling the same 失效
标题翻译：协处理器和方法，用于其控制。
公开(公告)号：EP0287115B1
公开(公告)日：1994-11-09
申请号：EP88106049.5
申请日：1988-04-15
申请人： HITACHI, LTD. , Hitachi Engineering Co., Ltd.
发明人： Morinaga, Shigeki , Nakagawa, Norio , Watabe, Mitsuru , Ohba, Mamoru , Kida, Hiroyuki , Kajiwara, Hisashi , Asai, Takeshi , Tatezaki, Junichi
IPC分类号： G06F9/38
CPC分类号： G06F9/3877 , G06F9/3885

7. 发明公开

EP0476478A2 Digital pulse processing device 失效
标题翻译： Digitale Impulsverarbeitungsvorrichtung。
公开(公告)号：EP0476478A2
公开(公告)日：1992-03-25
申请号：EP91115226.2
申请日：1991-09-09
申请人： HITACHI, LTD.
发明人： Ohba, Mamoru , Watabe, Mitsuru , Minami, Rika , Obara, Sanshiro
IPC分类号： G01P3/489
CPC分类号： G01P3/489
摘要： A digital pulse processing device is capable of selecting precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters 110 and 111 that can be separated from and coupled with each other, a mode control circuit 129 for instructing separation and coupling of the counters 110 and 111, and a control circuit 116 for separating and coupling the counters 110 and 111 in accordance with the instruction of the mode control circuit 129. An overflow condition of the timer 119 is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow. A register 128 is provided to hold the value of the timer 119 when a microcomputer reads in the counter 111. In this way, even when ΔA(i) = 0, speed detection operation can be executed using the value of the counter 111 obtained synchronously with the counting of the counter 110.
摘要翻译：数字脉冲处理装置能够选择精度。数字脉冲处理装置包括用于对从脉冲输出装置输出的脉冲进行计数的计数器组，该计数器组具有可以彼此分离和耦合的多个计数器110和111;用于指示分离的模式控制电路129，计数器110和111的耦合，以及用于根据模式控制电路129的指令分离和耦合计数器110和111的控制电路116.使用溢出标志检测定时器119的溢出状况。当溢出条件发生两次以上时，通过设置标志来进行溢出检测。通过软件重写标志的状态来重置该标志。以常规方式检测出第一次发生的溢出状况，并将其视为进位或借位。当计数器读入计数器111时，提供寄存器128以保持定时器119的值。这样，即使当DELTA A（i）= 0时，也可以使用获得的计数器111的值来执行速度检测操作与计数器110的计数同步。

8. 发明授权

EP0476478B1 Digital pulse processing device 失效
标题翻译：数字脉冲处理装置
公开(公告)号：EP0476478B1
公开(公告)日：1996-02-21
申请号：EP91115226.2
申请日：1991-09-09
申请人： HITACHI, LTD.
发明人： Ohba, Mamoru , Watabe, Mitsuru , Minami, Rika , Obara, Sanshiro
IPC分类号： G01P3/489
CPC分类号： G01P3/489

9. 发明授权

EP0371443B1 A saving and restoring method and a processor system for implementation of the same method 失效
标题翻译：救援和它后面的存储方法和处理器系统。
公开(公告)号：EP0371443B1
公开(公告)日：1995-04-12
申请号：EP89121903.2
申请日：1989-11-28
申请人： HITACHI, LTD.
发明人： Ohba, Mamoru , Morinaga, Shigeki , Watabe. Mitsuru , Kida, Hiroyuki
IPC分类号： G06F9/46
CPC分类号： G06F9/461 , G06F9/30025 , G06F9/3861 , G06F9/3885

10. 发明公开

EP0287115A3 Coprocessor and method of controlling the same 失效
标题翻译：共同控制器及其控制方法
公开(公告)号：EP0287115A3
公开(公告)日：1992-03-11
申请号：EP88106049.5
申请日：1988-04-15
申请人： HITACHI, LTD. , Hitachi Engineering Co., Ltd.
发明人： Morinaga, Shigeki , Nakagawa, Norio , Watabe, Mitsuru , Ohba, Mamoru , Kida, Hiroyuki , Kajiwara, Hisashi , Asai, Takeshi , Tatezaki, Junichi
IPC分类号： G06F9/38
CPC分类号： G06F9/3877 , G06F9/3885
摘要： The interface portion of a coprocessor is provided with a FIFO (500) (First-in First-Out) and means for accepting instructions in succession. The pipeline control of the instructions becomes possible in this way, and protocol means (200) associated with a microprocessor is also provided.

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