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1. 发明公开

EP0691763A2 Ranging for a telecommunications network 失效
标题翻译：在einem Nachrichten-Netzwerk的Abstands-Einmessung
公开(公告)号：EP0691763A2
公开(公告)日：1996-01-10
申请号：EP95304670.3
申请日：1995-07-04
申请人： GPT LIMITED
发明人： Proctor, Richard John , Maddern, Thomas Slade
IPC分类号： H04J3/06 , H04B10/20 , H04L1/00 , H04L1/08
CPC分类号： H04Q11/0478 , H04J3/0682 , H04J14/02 , H04J14/0298 , H04J14/08 , H04L1/004 , H04L7/048 , H04L2012/5605 , H04L2012/561 , H04L2012/5615 , H04L2012/5629 , H04L2012/5638
摘要： In a telecommunications time division multiplex (TDMA) optic network system, network termination equipments (NTE's) are enabled to communicate with a head end by the NTE encoding a message as a signal including error correction on the existing signal traffic, monitoring the errors at the head end and extracting the message from the errors.
摘要翻译：在电信时分多路复用（TDMA）光网络系统中，网络终端设备（NTE）能够通过NTE对头端进行编码，将消息编码为包括对现有信号业务的纠错的信号，监视在首先从错误中提取消息。

2. 发明公开

EP0554969A3 STM switching arrangement 失效
标题翻译： STM开关装置
公开(公告)号：EP0554969A3
公开(公告)日：1995-12-13
申请号：EP93300011.9
申请日：1993-01-04
申请人： GPT LIMITED
发明人： Jeffrey, Mark Timothy , Maddern, Thomas Slade , Proctor, Richard John
IPC分类号： H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04J2203/0005 , H04L12/6402 , H04L49/606 , H04L2012/5681 , H04Q11/0478
摘要： An STM telecommunications switch is provided, comprising a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a centrl switching unit to switch each input port to any output port and wherein the data is switched in octets.

3. 发明公开

EP0554969A2 STM switching arrangement 失效
标题翻译： STM-Vermittlungseinrichtung。
公开(公告)号：EP0554969A2
公开(公告)日：1993-08-11
申请号：EP93300011.9
申请日：1993-01-04
申请人： GPT LIMITED
发明人： Jeffrey, Mark Timothy , Maddern, Thomas Slade , Proctor, Richard John
IPC分类号： H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04J2203/0005 , H04L12/6402 , H04L49/606 , H04L2012/5681 , H04Q11/0478
摘要： An STM telecommunications switch is provided, comprising a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a centrl switching unit to switch each input port to any output port and wherein the data is switched in octets.
摘要翻译：提供STM通信交换机，其包括多个并行数据交换平面和并行控制平面，每个平面具有相等数目的输入端口和输出端口，以及一个中心切换单元，用于将每个输入端口切换到任何输出端口，并且其中，数据以八位字节切换。

4. 发明公开

EP0366263A2 Time division switch 失效
标题翻译： Zeitmultiplexkoppelnetz。
公开(公告)号：EP0366263A2
公开(公告)日：1990-05-02
申请号：EP89309656.0
申请日：1989-09-22
申请人： GPT LIMITED
发明人： Proctor, Richard John , Maddern, Thomas Slade , Philip, Alexander Schroder
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/255 , H04L2012/5649 , H04L2012/565 , H04L2012/5651
摘要： The invention concerns Asynchronous Time Division Switches particularly for packet switching. In one embodiment a switch has 256 ports running at 155 M bits and is capable of switching incoming data cells at each of the input ports to any one of 256 output ports. At each input port a switch sequentially distributes the received data cells over 16 outputs each of which is connected to a different DMR circuit. There are 256 DMR circuits each having 16 inputs and 16 outputs. A DMR circuit is a fixed space switching device which has N inputs, N time intervals and N outputs and operates cyclically so that each input goes to each output for 1/Nth of the time. The inner stage of the ATD switch comprises 256 central switches each having 16 inputs and 16 outputs. Each central stage switch has its 16 inputs connected to 16 different DMR circuits. The fourth stage of the switch consists of another array of 256 output DMR circuits with each central switch being connected to 16 different output DMR circuits. Each output DMR has its outputs connected to 16 different output ports. The internal circuitry of the ATD switch runs on 20 M bits. When a data cell is received at an input port its destination is derived from a header attached to the cell. Control circuitry enables the receiving port to request three address to query three possible routes through the switch. The ability to provide this series of questions is given by staggering the windows through which an output port can communicate with the central switches. Although data streams are received asynchronously the operation of the ATD switch is synchronous.
The switch is potentially capable of switching non ATD, synchronous traffic. Mixed mode of operation is possible.
摘要翻译：本发明涉及特别用于分组交换的异步时分交换机。在一个实施例中，交换机具有以155M位运行的256个端口，并且能够将每个输入端口处的输入数据单元切换到256个输出端口中的任一个。在每个输入端口，开关顺序地分配接收的数据单元超过16个输出，每个输出连接到不同的DMR电路。有256个DMR电路，每个具有16个输入和16个输出。 DMR电路是具有N个输入，N个时间间隔和N个输出的固定空间切换装置，并且周期性地进行操作，使得每个输入到达每个输出1 / Nth时间。 ATD开关的内部级包括256个中央开关，每个开关具有16个输入和16个输出。每个中央级开关的16个输入端连接到16个不同的DMR电路。开关的第四级由256个输出DMR电路的另一个阵列组成，每个中央开关连接到16个不同的输出DMR电路。每个输出DMR的输出连接到16个不同的输出端口。 ATD交换机的内部电路运行在20 M位。当在输入端口处接收到数据信元时，其目的地是从连接到该信元的报头导出的。控制电路使接收端口能够请求三个地址来查询交换机的三条可能的路由。提供这一系列问题的能力是通过交错输出端口可以与中央交换机通信的窗口进行交错给出的。虽然数据流是异步接收的，但是ATD交换机的操作是同步的。所描述的实施例具有许多优点：首先，ATD开关的设计是同步的，从而允许两个平面以双同步模式运行以检查故障。交换机通过在多个中央阶段传播数据，以比它接收的速率更低的速率切换数据。仅在交换机的接收部分需要控制，然后单元是自路由，具有多个中心路由。因此ATD交换机是自动路由。此外，交换机具有可变小区路由和小区序列完整性。这是一个非常不寻常的组合，但是非常可取。 ATD开关不需要非常高的技术来使其工作，它能够用当今的技术制造。另一个优点是在ATD交换机中描述的单元延迟是由三个元素构成的，一个FIXED延迟取决于端口号（0到256 us），纯ATD输出争用延迟（0到105 us，所有ATD交换机都有这个）和一个非常小的输入延迟（0到10 us）。大多数交换机具有许多阶段，每个阶段都表现出ATD输出争用延迟。最后，交换机潜在地可以切换非ATD，同步业务。混合操作模式是可能的。

5. 发明授权

EP0317055B1 Telecommunications digital switch 失效
标题翻译：数字通信开关。
公开(公告)号：EP0317055B1
公开(公告)日：1994-11-17
申请号：EP88307864.4
申请日：1988-08-25
申请人： GPT LIMITED
发明人： Maddern, Thomas Slade , Chopping, Geoffrey
IPC分类号： H04Q11/04
CPC分类号： H04Q11/08

6. 发明公开

EP0366263A3 Time division switch 失效
标题翻译：时间开关
公开(公告)号：EP0366263A3
公开(公告)日：1992-09-16
申请号：EP89309656.0
申请日：1989-09-22
申请人： GPT LIMITED
发明人： Proctor, Richard John , Maddern, Thomas Slade , Philip, Alexander Schroder
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/255 , H04L2012/5649 , H04L2012/565 , H04L2012/5651
摘要： The invention concerns Asynchronous Time Division Switches particularly for packet switching. In one embodiment a switch has 256 ports running at 155 M bits and is capable of switching incoming data cells at each of the input ports to any one of 256 output ports. At each input port a switch sequentially distributes the received data cells over 16 outputs each of which is connected to a different DMR circuit. There are 256 DMR circuits each having 16 inputs and 16 outputs. A DMR circuit is a fixed space switching device which has N inputs, N time intervals and N outputs and operates cyclically so that each input goes to each output for 1/Nth of the time. The inner stage of the ATD switch comprises 256 central switches each having 16 inputs and 16 outputs. Each central stage switch has its 16 inputs connected to 16 different DMR circuits. The fourth stage of the switch consists of another array of 256 output DMR circuits with each central switch being connected to 16 different output DMR circuits. Each output DMR has its outputs connected to 16 different output ports. The internal circuitry of the ATD switch runs on 20 M bits. When a data cell is received at an input port its destination is derived from a header attached to the cell. Control circuitry enables the receiving port to request three address to query three possible routes through the switch. The ability to provide this series of questions is given by staggering the windows through which an output port can communicate with the central switches. Although data streams are received asynchronously the operation of the ATD switch is synchronous. The switch is potentially capable of switching non ATD, synchronous traffic. Mixed mode of operation is possible.

7. 发明公开

EP0474429A1 An asynchronous transfer mode switching arrangement providing broadcast transmission 失效
标题翻译： Asynchrone-Transfermodus-Vermittlungseinrichtung mitRundsendeübertragung。
公开(公告)号：EP0474429A1
公开(公告)日：1992-03-11
申请号：EP91307880.4
申请日：1991-08-28
申请人： GPT LIMITED
发明人： Proctor, Richard John , Maddern, Thomas Slade
IPC分类号： H04L12/18 , H04L12/56
CPC分类号： H04L12/5601 , H04L12/18 , H04L49/108 , H04L49/203 , H04L49/309 , H04L2012/5681
摘要： An asynchronous transfer mode switching arrangement comprises a serial to parallel converter arranged to receive input packets of data, which include routing information, in serial form and convert the packets of data to parallel form. A random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output. The random access memory and the output queues are controlled by a memory management arrangement to which is connected a broadcast channel routine random access memory. The memory management arrangement addresses the broadcast channel routine random access memory with channel index information, and receives information identifying the required output ports.
摘要翻译：异步传输模式切换装置包括串行到并行转换器，其被布置为以串行形式接收包括路由信息的输入数据包，并将数据分组转换为并行形式。提供随机存取存储器，其中将每个数据包分组输入到存储器中的寻址位置，并且将该地址输入到尾部的相应先进先出输出队列中。访问队列头部的地址，并将数据包从随机存取存储器读取到并行到串行转换器中，并将数据包顺序传送到相关的输出。随机访问存储器和输出队列由连接有广播信道例程随机存取存储器的存储器管理装置控制。存储器管理装置利用信道索引信息寻址广播信道例程随机存取存储器，并且接收标识所需输出端口的信息。

8. 发明公开

EP0419019A1 Message routing check system 失效
标题翻译： Prüfungssystemfürdie Leitweglenkung von Nachrichten。
公开(公告)号：EP0419019A1
公开(公告)日：1991-03-27
申请号：EP90308558.7
申请日：1990-08-03
申请人： GPT LIMITED
发明人： Proctor, Richard John , Chopping, Geoffrey , Maddern, Thomas Slade
IPC分类号： H04L12/56 , H04L29/06 , H04Q11/04
CPC分类号： H04Q11/04 , H04L29/06 , H04L49/30 , H04L49/555
摘要： The invention concerns telecommunication apparatus in which data messages are routed across a switch. The messages are of the kind comprising a message portion and an incoming message identity portion and the apparatus comprising means (22, 23) for generating from the incoming message identity portion an outgoing message identity portion, means including a switch (21) utilising the incoming and outgoing message identity portions to route the message to an output port, and characterised in that the apparatus further comprises means (24, 25) for utilising the outgoing message identity portion to generate a further message identity portion and means (26, 27) for comparing the incoming and further message identity portions to detect faults.
摘要翻译：本发明涉及通过交换机路由数据消息的电信设备。所述消息是包括消息部分和传入消息标识部分的类型，并且所述装置包括用于从所述输入消息身份部分生成外向消息标识部分的装置（22,23），包括利用所述传入的交换机（21）的装置以及输出消息身份部分以将消息路由到输出端口，并且其特征在于，所述设备还包括用于利用所述传出消息身份部分来生成另外的消息身份部分的装置（24,25）以及用于比较传入和进一步的消息标识部分来检测故障。

9. 发明公开

EP0317055A2 Telecommunications digital switch 失效
标题翻译：数字电影Fernmeldekoppelfeld。
公开(公告)号：EP0317055A2
公开(公告)日：1989-05-24
申请号：EP88307864.4
申请日：1988-08-25
申请人： GPT LIMITED
发明人： Maddern, Thomas Slade , Chopping, Geoffrey
IPC分类号： H04Q11/04
CPC分类号： H04Q11/08
摘要： A telecommunications digital switch for switching channels of time division multiplexed (TDM) signals on a multiplicity of switch input and output paths, the switch comprising:
input and output switching stages and a central switching area:
the input and output switch stages each comprising arrays of DSM (as herein defined);
the central switching area comprising first and second arrays of DMR (as herein defined), wherein the DMR are so preprogrammed with a channel allocation address pattern that all channel routes through the central switching stage experience the same time delay;
the arrangement being such that all or a major part of the channel routes through the switch are constrained to have delays such that all channels are displaced to positions within (n) or (n + 1) subsequent time frames of the TDM system where (n) is an integer, selected from the range 0, 1, 2.
摘要翻译：一种用于在多个开关输入和输出路径上切换时分复用（TDM）信号的信道的电信数字开关，所述开关包括：输入和输出开关级和中央交换区域：所述输入和输出开关级各自包括： DSM（如本文定义）; 中央交换区域包括第一和第二DMR阵列（如此处所定义的），其中DMR如此预编程有通过中央交换级的所有信道路由经历相同的时间延迟的信道分配地址模式; 该布置使得通过交换机的信道路由的全部或大部分被限制为具有延迟，使得所有信道被移位到TDM系统的（n）或（n + 1）个后续时间帧内的位置，其中（n ）是一个整数，从0，1，2范围内选择。

10. 发明公开

EP0858192A2 An ATM switching arrangement 失效
标题翻译： ATM-Vermittlungsanordnung
公开(公告)号：EP0858192A2
公开(公告)日：1998-08-12
申请号：EP98106163.3
申请日：1992-08-03
申请人： GPT LIMITED
发明人： Jeffrey, Mark Timothy , Maddern, Thomas Slade , Proctor, Richard John
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04L12/1836 , H04L49/106 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/203 , H04L49/255 , H04L2012/5647 , H04L2012/565 , H04L2012/5651 , H04L2012/5681 , H04L2012/5684 , H04Q11/0478
摘要： An ATM telecommunications switch comprises a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port and further comprises means to connect data from a single timeslot on the central switching unit to a plurality of output ports in a point to multipoint operation.
There is further a multipoint memory for storing information regarding the data addresses and a forward transfer store to provide additional storage for multipoint cells.
摘要翻译： ATM电信交换机包括多个并行数据交换平面和并行控制平面，每个平面具有相等数量的输入端口和输出端口，以及中央交换单元，用于将每个输入端口切换到任何输出端口，并且还包括连接的装置数据从中央交换单元上的单个时隙到点对多点操作中的多个输出端口。还存在用于存储关于数据地址的信息的多点存储器和向前传送存储器，以为多点信元提供额外的存储。

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