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1. 发明公开

EP1556952A2 SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT 审中-公开
标题翻译：系统和方法在相LOOP降噪
公开(公告)号：EP1556952A2
公开(公告)日：2005-07-27
申请号：EP03779214.0
申请日：2003-10-23
申请人： GCT Semiconductor, Inc.
发明人： AHN, Youngho , SONG, Eunseok , KOO, Yido , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H03L7/06
CPC分类号： H03L7/1978
摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

2. 发明授权

EP1371167B1 FRACTIONAL-N FREQUENCY SYNTHESIZER WITH FRACTIONAL COMPENSATION METHOD 有权
标题翻译：具有分数补偿方法分数N频率合成器
公开(公告)号：EP1371167B1
公开(公告)日：2008-03-05
申请号：EP02723501.9
申请日：2002-03-20
申请人： GCT Semiconductor, Inc.
发明人： HUH, Hyungki , SONG, Eunseok , LEE, Kang Yoon , KOO, Yido , LEE, Jeongwoo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H04L7/00 , H03L7/087 , H03L7/197 , H03L7/089 , H03L7/091 , H03L7/095
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/0898 , H03L7/095
摘要： A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.

3. 发明授权

EP1514351B1 LC OSCILLATOR WITH WIDE TUNING RANGE AND LOW PHASE NOISE 有权
标题翻译：与大的调谐和低相位噪声LC振荡器
公开(公告)号：EP1514351B1
公开(公告)日：2007-11-21
申请号：EP03728954.3
申请日：2003-06-05
申请人： GCT Semiconductor, Inc.
发明人： KOO, Yido , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H03L7/08 , H03B5/08 , H03L7/099
CPC分类号： H03L7/099 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03B2201/025 , H03J2200/10
摘要： A voltage-controlled oscillator (600) including an active oscillator circuit (610), an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator (600). Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit (610). To avoid damage to the switches in the capacitive circuits, the capacitive circuits further comprise resistors (622). The resistors can be configured in several different ways so that the voltage-controlled oscillator (600) can have a high degree of reliability, and a wide tuning range with constant phase noise performance.

4. 发明公开

EP1527522A1 AN RF FRONT END WITH REDUCED CARRIER LEAKAGE 审中-公开
标题翻译：具有减少残留载波RF输入级
公开(公告)号：EP1527522A1
公开(公告)日：2005-05-04
申请号：EP03771871.5
申请日：2003-07-28
申请人： GCT Semiconductor, Inc.
发明人： SONG, Eunseok , LEE, Seung-Wook , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H04B1/00 , H04B1/26
CPC分类号： H04B1/28 , H04B1/525
摘要： A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider (407) that divides an input signal frequency by a predetermined value to produce an output signal frequency (417); and a frequency mixer (405, 406) that mixes the output signal frequency (417) with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency (417) and the carrier signal frequency. The predetermined value and the input signal frequency are selected such that the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency (417). The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.

5. 发明授权

EP1374439B1 AUTOMATIC GAIN CONTROL METHOD FOR HIGHLY INTEGRATED COMMUNICATION RECEIVER 有权
标题翻译：自动增益控制方法对于高集成通信接收机
公开(公告)号：EP1374439B1
公开(公告)日：2009-12-02
申请号：EP02757777.4
申请日：2002-03-27
申请人： GCT Semiconductor, Inc.
发明人： KANG, Suwon , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H03G3/30
CPC分类号： H03G3/3068

6. 发明公开

EP1803216A2 SIGMA-DELTA BASED PHASE LOCK LOOP 审中-公开
标题翻译：相回路ONΣ-ΔBASE
公开(公告)号：EP1803216A2
公开(公告)日：2007-07-04
申请号：EP05802909.1
申请日：2005-09-21
申请人： GCT Semiconductor, Inc.
发明人： KOO, Yido , AHN, Youngho, 418-102 Samsung Raemiahn 4 Apt. , SONG, Eunseok , LEE, Jeong-Woo, 101-204 Samhwan Apt. , PARK, Joonbae , LEE, Kyeongho, 401 Shindongkwang Villa 108-8
IPC分类号： H03D3/24
CPC分类号： H03L7/0895 , H03L7/1976
摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PDF to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

7. 发明公开

EP1557021A1 COMMUNICATION TRANSMITTER USING OFFSET PHASE-LOCKED-LOOP 审中-公开
标题翻译：有偏移相位控制环路沟通渠道
公开(公告)号：EP1557021A1
公开(公告)日：2005-07-27
申请号：EP03783099.9
申请日：2003-10-31
申请人： GCT Semiconductor, Inc.
发明人： LEE, Kang-Yoon , SONG, Eunseok , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H04L27/20 , H04L27/04 , H04L27/12
CPC分类号： H03C3/0966 , H03C3/0933
摘要： A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal is generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, and then using a frequency divider in a feedback loop to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizing the number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.

8. 发明公开

EP1433250A1 AN ADAPTIVE LINEARIZATION TECHNIQUE FOR COMMUNICATION BUILDING BLOCK 审中-公开
标题翻译：通信建筑模块的自适应线性化技术
公开(公告)号：EP1433250A1
公开(公告)日：2004-06-30
申请号：EP02759481.1
申请日：2002-08-29
申请人： GCT Semiconductor, Inc.
发明人： JEONG, Hei-Sam,198-13, Jina High Vil Apt , PARK, Joonbae , LEE, Kyeongho,Samsung-san-Jookong Apt.
IPC分类号： H03F1/26
CPC分类号： H03F1/3223 , H03F1/3229
摘要： The present invention is directed to a linearization apparatus and method. Preferred embodiments according to the present invention can combine an auxiliary non-linear block (300) to a functional block of a system to increase linearity of an output signal (520) of the system such as a communication system. System overhead due to the non-linear auxiliary block can be small because of circuit structure, cost and low consumption. Further, the non-linear auxiliary block can be designed so that no feedback path is required. Further preferred embodiments can use a feedback path without loss of stability by using a cancellation apparatus or process based on an averaging detection of the output signal. For example, a feedback loop can detect power leakage in a sideband caused by non-linearities of the communication system.
摘要翻译：本发明涉及一种线性化装置和方法。根据本发明的优选实施例可以将辅助非线性块（300）组合到系统的功能块，以增加系统（例如通信系统）的输出信号（520）的线性度。由于电路结构，成本和低消耗，由于非线性辅助块引起的系统开销可能很小。此外，非线性辅助块可以设计成不需要反馈路径。进一步优选的实施例可以通过使用消除设备或基于输出信号的平均检测的处理来使用反馈路径而不会失去稳定性。例如，反馈回路可以检测由通信系统的非线性引起的边带中的功率泄漏。

9. 发明授权

EP1374396B1 VARIABLE GAIN LOW-NOISE AMPLIFIER FOR A WIRELESS TERMINAL 有权
标题翻译：低噪声放大器具有可变增益的无线终端
公开(公告)号：EP1374396B1
公开(公告)日：2009-05-06
申请号：EP02757825.1
申请日：2002-03-28
申请人： GCT Semiconductor, Inc.
发明人： JEONG, Hoe-Sam, Seoul Natl. Univ. , LEE, Seung-Wook , LEE, Won-Seok , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H03G1/00
CPC分类号： H03F1/223 , H03F3/195 , H03F3/72 , H03F2200/294 , H03F2200/378 , H03F2200/391 , H03F2200/451 , H03F2203/7236 , H03G1/0088
摘要： A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier (MN1) may achieve variable gain by deploying a network of transistors (MP1-MPn) in a parallel array, each independently selectable by a PMOS switch (220), and providing the variable resistance for the resonant circuit (Rp, Lp). Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch (220). The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors (Cp'1-Cp'n).

10. 发明公开

EP1665557A2 SYSTEM AND METHOD FOR FILTERING SIGNALS IN A TRANSCEIVER 有权
标题翻译：系统及方法的发射机/接收机的信号滤波
公开(公告)号：EP1665557A2
公开(公告)日：2006-06-07
申请号：EP04782302.6
申请日：2004-08-27
申请人： GCT Semiconductor, Inc.
发明人： JEON, Young-Deuk , LEE, Seung-Wook , LEE, Jeong-Woo , PARK, Joonbae , LEE, Kyeongho
IPC分类号： H04B1/38
CPC分类号： H04B1/1027 , H03H11/1252 , H03H11/1291 , H03J1/0008 , H04B1/44
摘要： A system and method for filtering signals in a communications system reduces hardware and chip size requirements by selectively connecting a filter along transmitter and receiver paths of a transceiver. In operation, a controller generated signals for connecting the filter along the transmitter path when the transceiver is in transmitter mode and for connecting the filter along the receiver path when the transmitter is in receiver mode. The controller then generates additional signals for setting one or more parameters of the filter based on the path connected, or put differently based on the operational mode of the transceiver. In a variation, the controller sets the parameters of additional elements coupled to the filter as a way of further controlling processing of the transmitter and receiver signals. The system and method are particularly well suited to controlling the filtering of signals at the front-end of the transceiver having a direct-conversion architecture and in general ones performing time-multiplexing applications.

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