会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 8. 发明公开
    • PROCESSING DEVICE BY PREDICTING BRANCH FROM COMPRESSED ADDRESS INFORMATION
    • 处理设备通过预测JUNCTION压缩地址信息学报
    • EP1990714A4
    • 2009-04-29
    • EP06714899
    • 2006-02-28
    • FUJITSU LTD
    • YOKOI MEGUMIUKAI MASAKISUZUKI TAKASHI
    • G06F9/38
    • G06F9/3806G06F9/322G06F9/324G06F9/3844
    • A processing device comprises an acquiring section to acquire an instruction at an acquisition stage, an address control section to determine an instruction address of an original memory for the instruction acquired by the acquiring section, a branch instruction predicting section to predict whether an instruction to be executed in the next execution stage is a branch instruction or not in accordance with instruction history information processed in the past, and an executing section to execute at least one instruction at the execution stage. The address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in the instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. The branch instruction predicting section includes a history memory section that stores the higher-order bit part corresponding to a branch address of a processed branch instruction and the lower-order bit part at either one of a plurality of storing places determined from the higher-order bit part corresponding to a branch address of a processed branch instruction and the lower-order bit part.