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1. 发明公开

EP2892252A4 COMMUNICATION DEVICE, SYSTEM, AND COMMUNICATION METHOD 有权
标题翻译：通信设备，系统和通信过程
公开(公告)号：EP2892252A4
公开(公告)日：2015-09-16
申请号：EP12883686
申请日：2012-08-28
申请人： FUJITSU LTD
发明人： YAMAUCHI HIROMASA , YAMASHITA KOICHIRO , SUZUKI TAKAHISA , KURIHARA KOJI , OTOMO TOSHIYA , TERANISHI YUTA
IPC分类号： H04W4/04 , H04W52/02 , H04W84/18
CPC分类号： H04W52/0258 , H04W52/0277 , H04W84/18 , Y02D70/00
摘要： A sensor node (101-i) is assumed to be able to execute any one among a first operation by which another sensor node (101) is requested to execute data process and if the request is not accepted the sensor node (101-i) starts executing the data processing after waiting for charging and a second operation by which the sensor node (101-i) starts executing the data processing after waiting for charging, without requesting the data processing to be executed. The sensor node (101-i) compares an expected value of a first time that elapses until execution is started by the sensor node (101-i) or the other sensor node (101) when the first operation is executed, and a second time that elapses until execution is started by the sensor node (101-i) when the second operation is executed. Based on the comparison result, the sensor node (101-i) executes among the first operation and the second operation, the operation for which the time that elapses until execution is started is shorter.
摘要翻译：假设传感器节点（101-i）能够执行另一传感器节点（101）被请求执行数据处理的第一操作中的任一个，并且如果该请求不被接受，则传感器节点（101-i）在等待充电之后开始执行数据处理，以及在等待充电之后传感器节点（101-i）开始执行数据处理的第二操作，而不请求执行数据处理。传感器节点（101-i）在执行第一操作时比较经过的第一次的期望值，直到传感器节点（101-i）或其他传感器节点（101）开始执行，并且第二次当执行第二操作时，经过传感器节点（101-i）开始执行。基于比较结果，传感器节点（101-i）在第一操作和第二操作之间执行，直到执行开始经过的时间的操作较短。

2. 发明公开

EP2876949A4 POSITION ESTIMATION METHOD, SYSTEM, AND POSITION ESTIMATION DEVICE 审中-公开
标题翻译：位置评估方法，系统和位置估计装置
公开(公告)号：EP2876949A4
公开(公告)日：2015-08-05
申请号：EP12881486
申请日：2012-07-18
申请人： FUJITSU LTD
发明人： TERANISHI YUTA , YAMASHITA KOICHIRO , SUZUKI TAKAHISA , YAMAUCHI HIROMASA , KURIHARA KOJI , OTOMO TOSHIYA
IPC分类号： H04W64/00 , G01S5/02 , H04L29/08 , H04W4/00 , H04W4/04 , H04W84/18
CPC分类号： H04W64/006 , G01S5/0278 , G01S5/0284 , G01S5/0289 , H04L67/12 , H04W4/005 , H04W64/00 , H04W84/18
摘要： A position estimation apparatus (100) acquires, for base devices (102), the number of hops from a target sensor node (101) to a base device (102). The position estimation apparatus (100) calculates, for each base device (102), a distribution of estimated distances corresponding to the total hops, based on the number of hops and a distribution of estimated distances stored in a storage device (110). The position estimation apparatus (100) calculates, for each base device (102), a distribution of estimated positions within a given region (A), based on the distribution of estimated distances, information concerning a range of the given region (A), and information concerning a position of the base device (102). The position estimation apparatus (100) calculates an index that indicates a probability of a position of the target sensor node (101) within the given region (A), based on the sum of distributions of estimated positions concerning the base stations.

3. 发明公开

EP2600245A4 MULTI-CORE PROCESSOR SYSTEM, ALLOCATION PROGRAM, CONTROL PROGRAM, ALLOCATION METHOD AND CONTROL METHOD 审中-公开
标题翻译：多核处理器系统中，分配程序控制程序分配过程和控制方法
公开(公告)号：EP2600245A4
公开(公告)日：2013-11-06
申请号：EP10855322
申请日：2010-07-30
申请人： FUJITSU LTD
发明人： YAMASHITA KOICHIRO , SUZUKI TAKAHISA , YAMAUCHI HIROMASA , KURIHARA KOJI
IPC分类号： G06F9/48 , G06F1/08 , G06F1/32 , G06F9/50
CPC分类号： G06F13/34 , G06F1/324 , G06F1/329 , G06F9/4812 , G06F9/5033 , G06F13/24 , G06F13/26 , Y02D10/126 , Y02D10/22 , Y02D10/24
摘要： A CPU #0 detects an assignment instruction for a process 1. The CPU #0 acquires a remaining time obtained by subtracting a CP of a handler B (processing time of handler A) from a period (Dt of handler B) that is from the time when an event of the handler B occurs, which is interrupt processing assigned to a CPU #1. The CPU #0 judges if the acquired remaining time is greater than or equal to a processing time (CP of process 1) defined to limit an interrupt in the process. In other words, when the process 1 is assigned to the CPU #1, even if an event of the handler B occurs during execution of the process 1, the CPU #0 judges whether the Dt of the handler B can be met. When the event of the handler B occurs during execution of the process 1, the CPU #0 judges that the Dt of the handler B can be met and therefore, the CPU #0 assigns the process 1 to the CPU #1.

4. 发明公开

EP2546744A4 SOFTWARE CONTROL DEVICE, SOFTWARE CONTROL METHOD, AND SOFTWARE CONTROL PROGRAM 有权
标题翻译：软件控制装置，软件控制程序和控制软件程序
公开(公告)号：EP2546744A4
公开(公告)日：2013-08-07
申请号：EP10847445
申请日：2010-03-11
申请人： FUJITSU LTD
发明人： YAMASHITA KOICHIRO , YAMAUCHI HIROMASA , MIYAZAKI KIYOSHI , SUZUKI TAKAHISA , KURIHARA KOJI
IPC分类号： G06F9/50
CPC分类号： G06F9/4881 , G06F2209/485
摘要： In a software control device, CPU (#0) uses a control instructing unit (303) to instruct CPU (#1) to temporarily suspend running software or decrease the execution priority. CPU (#1) having received the instruction, uses a determining unit (306) to determine whether starting software and the running software are accessing the same common resource. Upon determining that both are accessing the same common resource, CPU (#1) uses a control unit (307) to temporarily suspend the executing software or decrease the execution priority.

5. 发明公开

EP2669805A4 MEMORY CONTROL METHOD AND SYSTEM 审中-公开
标题翻译：存储器控制方法和系统
公开(公告)号：EP2669805A4
公开(公告)日：2016-08-31
申请号：EP11857205
申请日：2011-01-25
申请人： FUJITSU LTD
发明人： YAMAUCHI HIROMASA , YAMASHITA KOICHIRO , SUZUKI TAKAHISA , KURIHARA KOJI , OTOMO TOSHIYA
IPC分类号： G06F12/00 , G06F9/445 , G06F9/50 , G06F12/02 , G06F12/08 , G06F12/10 , G06F15/167 , G11C7/10
CPC分类号： G11C7/1075 , G06F9/445 , G06F9/5016 , G06F12/0284 , G06F12/08 , G06F12/10 , G06F12/1009 , G06F12/1018 , G06F15/167 , G06F15/7807 , G06F2212/1016

6. 发明公开

EP2562617A4 MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD 审中-公开
标题翻译：多核处理器系统的控制程序和控制方法
公开(公告)号：EP2562617A4
公开(公告)日：2016-03-23
申请号：EP10850237
申请日：2010-04-22
申请人： FUJITSU LTD
发明人： SUZUKI TAKAHISA , YAMASHITA KOICHIRO , YAMAUCHI HIROMASA , KURIHARA KOJI
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3284 , G06F1/3287 , G06F11/3423 , G06F2201/81 , H04W52/028 , Y02D10/126 , Y02D10/171 , Y02D70/00
摘要： A memory unit stores the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations. An OS (121) updates the number of time intervals; specifies a time stretch during which the number of time intervals stays abode a threshold; and sets, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power. When an operation is newly detected, the OS (121) sets a first power supply mode in which at least two cores are supplied with power, and switches, when the time interval goes beyond the time stretch, the first power supply mode to a second power supply mode in which less cores are supplied with power than in first power supply mode.

7. 发明公开

EP2879412A4 COMMUNICATION DEVICE, SYSTEM AND COMMUNICATION METHOD 有权
标题翻译：通信设备，系统和通信方法
公开(公告)号：EP2879412A4
公开(公告)日：2015-07-22
申请号：EP12881730
申请日：2012-07-24
申请人： FUJITSU LTD
发明人： KURIHARA KOJI , YAMASHITA KOICHIRO , SUZUKI TAKAHISA , YAMAUCHI HIROMASA , OTOMO TOSHIYA , TERANISHI YUTA
IPC分类号： H04W4/04 , H04L12/801 , H04L12/841 , H04L29/08 , H04W84/18
CPC分类号： H04Q9/00 , H04L45/22 , H04L45/24 , H04L47/125 , H04L47/28 , H04L67/1002 , H04L67/12 , H04L67/325 , H04W4/005 , H04W4/006 , H04W84/18
摘要： A sensor node (101-k) detects an occurrence of sensing (ev) and judges whether data processing corresponding to the sensing (ev) will finish before an occurrence of sensing (ev) subsequent to the sensing (ev), based on a time interval when the occurrence of the sensing (ev) is detected. When determining that the data processing will finish, the sensor node (101-k) executes the data processing and transmits the execution result of the data processing to a first apparatus (101-1) directly communicable with the sensor node (101-k). When determining that the data processing will not finish, the sensor node (101-k) transmits, to the first apparatus (101-1), request information causing the first apparatus (101-1) to execute the data processing and to transmit the execution result of the data processing to a second apparatus directly communicable with the first apparatus (101-1).

8. 发明公开

EP2555112A4 MULTI-CORE PROCESSOR SYSTEM, POWER CONTROL METHOD, AND POWER CONTROL PROGRAM 审中-公开
标题翻译：多核处理器系统中，功率控制方法和功率控制方法
公开(公告)号：EP2555112A4
公开(公告)日：2014-08-13
申请号：EP10848962
申请日：2010-03-31
申请人： FUJITSU LTD
发明人： KURIHARA KOJI , YAMASHITA KOICHIRO , MIYAKO KAZUMI
IPC分类号： G06F9/50
CPC分类号： G06F9/4881 , G06F9/5044 , G06F9/5094 , G06F9/52 , Y02D10/22
摘要： An APL (103), via a detecting unit (202), detects that a core different from a specific core executing a specific process currently executes software that is among plural software and different from specific software that is among the plural software and has a function equivalent to the specific process; via an extracting unit (203), extracts from a software capacity requirement table (201) storing required computing capacities for the plural software, requirement values indicating the required computing capacity of the specific software and of the software; uses the extracted requirement values and when a surplus judging unit (204) judges that a sum of the required computing capacities of the specific software and the software is at most a computing capacity value of the core, via an assigning unit (205), assigns the specific software to the core; and via a PMU (102), suspends the DSP (104).

9. 发明公开

EP2657840A4 MULTI-CORE PROCESSOR SYSTEM AND POWER CONTROL METHOD 审中-公开
标题翻译：多核心处理器的系统和方法的功率控制
公开(公告)号：EP2657840A4
公开(公告)日：2016-09-28
申请号：EP10861165
申请日：2010-12-22
申请人： FUJITSU LTD
发明人： SUZUKI TAKAHISA , YAMASHITA KOICHIRO , YAMAUCHI HIROMASA , KURIHARA KOJI , HAYAKAWA FUMIHIKO , ODATE NAOKI , HIRAKI TETSUO , OTOMO TOSHIYA
IPC分类号： G06F9/48 , G06F1/32 , G06F9/52
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , G06F9/526 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： When access contention by cores occurs at a device, processing performance is maintained and power consumption is reduced. A CPU (#0), via a detecting unit (307), detects the CPU (#0) and a CPU (#1), which form a predetermined core group that causes access contention at a device (#H0) in a device group (205). The CPU (#0), via an identifying unit (309), identifies the access contention state at the device (#H0) in the device group (205). The CPU (#0), from a clock frequency table (301), extracts according to the access contention state at the device (#H0), a clock frequency for the device (#H0) and a clock frequency for the CPUs (#0) and (#1). The CPU (#0) causes the device (#H0) to operate at the clock frequency for the device (#H0) and causes the CPUs (#0) and (#1) to operate at the clock frequency for the predetermined core group.

10. 发明公开

EP2590083A4 DATA RESTORATION PROGRAM, DATA RESTORATION DEVICE, AND DATA RESTORATION METHOD 审中-公开
标题翻译：数据恢复方案数据恢复装置和数据恢复过程
公开(公告)号：EP2590083A4
公开(公告)日：2016-04-20
申请号：EP10854080
申请日：2010-06-30
申请人： FUJITSU LTD
发明人： SUZUKI TAKAHISA , YAMASHITA KOICHIRO , YAMAUCHI HIROMASA , KURIHARA KOJI
IPC分类号： G06F12/16 , G06F1/30 , G06F11/10 , G06F12/06 , G06F12/08 , G06F15/167
CPC分类号： G06F1/30 , G06F11/1004 , G06F11/1076 , G06F12/0646 , G06F12/0804 , G06F2211/1059 , G06F2212/1028 , G06F2212/254
摘要： After electrical power supply to a CPU #1 and a local memory 1 is suspended, a data restoration apparatus (110) restores contents of the local memory onto a shared memory (104) from redundant data as a process at step S1. For example, DATA 2 stored in the local memory 1 is restored from DATA 1, DATA 3, and Parity 1 and stored into an saving area #1 in the shared memory (104). After the restoration at step S1, the data restoration apparatus (110) reconstructs parity data according to the number of operating CPUs as a process at step S2.

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