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1. 发明公开

EP1041763A2 Unequal error protection in multi-carrier transmission 有权
标题翻译： Ungleicher Fehlerschutz beiMehrträgerübertragung
公开(公告)号：EP1041763A2
公开(公告)日：2000-10-04
申请号：EP00100115.5
申请日：2000-01-05
申请人： FUJITSU LIMITED
发明人： Yoshida, Makoto , Ishizu, Eizou
IPC分类号： H04L1/00 , H04L27/26
CPC分类号： H04L1/0057 , H04L1/0042 , H04L1/007 , H04L27/2602 , H04L27/2617
摘要： A method of providing unequal error protection in a multi-carrier transmission includes the steps of coding data by a coding process of a given minimum code distance as measured in block codes comprised of modulated-signal points of sub-carriers, and changing the minimum code distance for each multi-carrier-symbol duration by changing the coding process.
摘要翻译：一种在多载波传输中提供不相等错误保护的方法包括以下步骤：通过由包括子载波的调制信号点的块码测量的给定最小码距离的编码处理来对数据进行编码，并且改变最小码通过改变编码过程对每个多载波符号持续时间的距离。

2. 发明公开

EP0023118A1 Integrated semiconductor devices 失效
标题翻译：集成半导体器件
公开(公告)号：EP0023118A1
公开(公告)日：1981-01-28
申请号：EP80302374.6
申请日：1980-07-15
申请人： FUJITSU LIMITED
发明人： Ohba, Osamu , Yoshida, Makoto
IPC分类号： H03K19/092 , H03K19/091 , H01L27/02 , H03K19/088
CPC分类号： H01L27/11898 , H03K19/01806
摘要： The device has a chip (A) with a functional circuit (FUN) in a central area and input (ii) and output (lo) interface circuits in peripheral areas.
Each interface circuit (li, lo) is built up by a group of circuit elements. The circuit elements are the same for each group and provide an input stage (F 1 ) an intermediate amplifying stage (F 2 ) and an output stage (F 3 ). By connecting the circuit elements of a group in different ways either an input (li) or an output (lo) interface circuit can be provided. Also, different threshold values for signals incoming to the interface circuit can be provided.
摘要翻译：该器件具有在中心区域具有功能电路（FUN）的芯片（A），以及在外围区域具有输入（ii）和输出（lo）接口电路。每个接口电路（li，lo）由一组电路元件构成。电路元件对于每个组是相同的，并且提供输入级（F1），中间放大级（F2）和输出级（F3）。通过以不同的方式连接组的电路元件，可以提供输入（Ii）或输出（Io）接口电路。而且，可以提供输入到接口电路的信号的不同阈值。

3. 发明授权

EP2291047B1 Mobile Communication Apparatus, Communication Method, and Communication System 有权
标题翻译：移动通信设备，通信方法和通信系统
公开(公告)号：EP2291047B1
公开(公告)日：2017-09-20
申请号：EP10170536.6
申请日：2010-07-22
申请人： FUJITSU LIMITED
发明人： Nakaya, Yuuta , Iida, Ichiro , Fujino, Nobutsugu , Yoshida, Makoto , Machida, Mamoru , Moriya, Masayoshi , Ushiki, Kazumasa
IPC分类号： H04W4/04 , H04W74/08
CPC分类号： H04W74/0816 , H04B17/27 , H04W4/046

4. 发明授权

EP1750410B1 OFDM receiving method and apparatus 有权
标题翻译：一种用于接收的方法和装置的OFDM
公开(公告)号：EP1750410B1
公开(公告)日：2013-03-27
申请号：EP06021130.7
申请日：2002-04-05
申请人： FUJITSU LIMITED
发明人： Yoshida, Makoto , Tanaka, Yoshinori
IPC分类号： H04L27/26 , H04B7/08
CPC分类号： H04L27/2647 , H04B7/0814 , H04B7/086 , H04B7/088 , H04B17/3911

5. 发明公开

EP2375656A1 Wireless communication apparatus and data relay method 审中-公开
标题翻译： Drahtlose Kommunikationsvorrichtung und Datenrelaisverfahren
公开(公告)号：EP2375656A1
公开(公告)日：2011-10-12
申请号：EP11156288.0
申请日：2011-02-28
申请人： Fujitsu Limited
发明人： Wen, Yun , Fujita, Hiroshi , Yoshida, Makoto
IPC分类号： H04L12/56 , H04W40/12
CPC分类号： H04L47/10 , H04L45/302 , H04L47/14 , H04L47/24
摘要： An optimum path storage unit (10) stores optimum paths on all wireless communication devices that can be destinations of data. A reception unit (20) receives relay data as a relay target. A QoS judgment unit (30) reads out an optimum path corresponding to a QoS requirement of relay data from the optimum path storage unit (10) and judges whether or not the QoS requirement of data is satisfied by the optimum path. The QoS judgment unit (30) outputs the relay data to a transmission unit (40) when it is judged such that the QoS requirement is satisfied. The transmission unit (40) transmits the relay data to the next node on the optimum path. When the QoS requirement of the relay data is not satisfied by the optimum path, a NACK information generation unit (50) generates NACK information that includes the fact that transmission of the relay data has been interrupted and transmits the NACK information to neighboring wireless communication devices.
摘要翻译：最佳路径存储单元（10）在可以是数据目的地的所有无线通信设备上存储最佳路径。接收单元（20）接收作为中继对象的中继数据。 QoS判断单元（30）从最优路径存储单元（10）读出与中继数据的QoS要求对应的最优路径，并判断数据的QoS要求是否满足最优路径。当判断为满足QoS要求时，QoS判断单元（30）将中继数据输出到发送单元（40）。发送单元（40）将中继数据发送到最佳路径上的下一个节点。当不满足最佳路径的中继数据的QoS要求时，NACK信息生成单元（50）生成包含中继数据的发送已中断的事实的NACK信息，并将NACK信息发送给相邻的无线通信装置。

6. 发明公开

EP0944200A3 Adaptive modulation method and apparatus 有权
标题翻译：自适应调制的方法和系统
公开(公告)号：EP0944200A3
公开(公告)日：2006-05-24
申请号：EP99104053.6
申请日：1999-03-17
申请人： FUJITSU LIMITED
发明人： Yoshida, Makoto
IPC分类号： H04L1/12 , H04L27/00
CPC分类号： H04L27/0012 , H04L1/0003 , H04L1/0032 , H04L1/0038 , H04L1/0047 , H04L1/0059
摘要： Each modulation level estimating unit calculates mean or variance of a carrier wave power for received signals to which no modulation level information is added when being transmitted, and calculates the difference between the calculated mean or variance and a mean or variance at each modulation level, as one of likelihood function values Λ ML#1 through Λ ML#X of each modulation level. A maximum likelihood function value selector selects the modulation level corresponding to the likelihood function value having the maximum likelihood value from among the likelihood function values, and makes a data selector select as a demodulation signal the output of a modulation level demodulating unit, which corresponds to the selected modulation level.

7. 发明公开

EP0827309A3 Coded modulation using repetition and tree codes 失效
标题翻译：编码调制重复和Baumkoden
公开(公告)号：EP0827309A3
公开(公告)日：2000-10-18
申请号：EP97105122.2
申请日：1997-03-26
申请人： FUJITSU LIMITED
发明人： Yoshida, Makoto
IPC分类号： H04L27/18 , H04L27/34
CPC分类号： H04L27/3416 , H04L27/186
摘要： A transmitter includes a repetition encoder (11) generating a repetition code sequence having a word length of r bits by carrying out a repetition coding with respect to 1 bit of a transmission unit which divides transmission information by a predetermined word length, where a rate of the repetition coding is set equal to a reciprocal of a predetermined integer r, a tree encoder (12) generating a tree code sequence by carrying out a tree coding with respect to the other bits of the transmission unit, where a rate of the tree coding is set to k/n, k denotes an information block length and n denotes a code block length, a mapping part (13) carrying out a mapping with respect to a combination of the repetition code sequence generated by the repetition encoder and the tree code sequence generated by the tree encoder, based on a set partitioning while maintaining correspondence between the mapping and the transmission unit, and a modulator (14) generating a transmitting wave signal by carrying out an M-ary modulation scheme with respect to a carrier wave signal based on the combination which is mapped by the mapping part, and transmitting the transmitting wave signal to a radio channel. The predetermined word length is (1+rk/N) bits, and N denotes a number of transmission symbols indicated by a single branch of a trellis diagram indicating a sequence of the tree code sequence. The modulator (14) modulates the carrier wave signal by 2 (1+n/N) levels.

8. 发明公开

EP0382504A3 Semiconductor integrated circuit having interconnection with improved design flexibility 失效
标题翻译：具有改进设计灵活性的互连的半导体集成电路
公开(公告)号：EP0382504A3
公开(公告)日：1992-08-26
申请号：EP90301286.2
申请日：1990-02-07
申请人： FUJITSU LIMITED
发明人： Suzuki, Kouichi , Miyoshi, Norihito , Yoshida, Makoto , Kokado, Masayuki
IPC分类号： H01L23/522 , H01L29/06 , H01L27/06 , H01L23/58
CPC分类号： H01L24/05 , H01L23/5221 , H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/0652 , H01L29/0646 , H01L29/0649 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/48227 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor integrated circuit comprises a substrate (51) of a first semiconductor type doped by a first impurity element with a first impurity density, the first semiconductor type being one of p-type and n-type semiconductors, a conductive layer (50) formed on a back surface of the substrate, a first layer (52) of a second semiconductor type doped by a second impurity element different from the first impurity element and formed on a front surface of the substrate, the second semiconductor type being the other of the p-type and n-type semiconductors and the first layer having a second impurity density lower than the first impurity density, a second layer (53) of the first semiconductor type formed on the first layer for forming circuit elements therein, a first region (54) of the second semiconductor type extending from a top surface of the first layer and reaching a top surface of the second layer, and a second region (55) of the first semiconductor type extending from a top surface of the substrate and reaching the top surface of said second layer, the first layer and the second region forming a conductive path for supplying a power source voltage to the circuit elements in the second layer from the back surface of the substrate.
摘要翻译：半导体集成电路包括由具有第一杂质浓度的第一杂质元素掺杂的第一半导体类型的衬底（51），第一半导体类型是p型和n型半导体之一，形成导电层（50）在所述基板的背面上形成由第二杂质元素掺杂的第二半导体型第一层（52），所述第二杂质元素与所述第一杂质元素不同，并形成在所述基板的前表面上，所述第二半导体类型是所述第二半导体类型 p型和n型半导体，第一层具有低于第一杂质浓度的第二杂质密度，第一半导体层的第二层（53）形成在第一层上，用于在其中形成电路元件，第一区（ 54），其从第一层的顶表面延伸并到达第二层的顶表面;以及第一半导体类型的第二区域（55），其从顶部冲浪并且到达所述第二层的顶表面，所述第一层和所述第二区域形成用于从所述衬底的所述背面向所述第二层中的所述电路元件提供电源电压的导电路径。

9. 发明公开

EP0174236A1 Semiconductor integrated circuit device having a test circuit 无效
标题翻译： Integrierte Halbleiterschaltung mit einerPrüfschaltung。
公开(公告)号：EP0174236A1
公开(公告)日：1986-03-12
申请号：EP85401583.1
申请日：1985-08-02
申请人： FUJITSU LIMITED
发明人： Ohba, Osam , Yoshida, Makoto
IPC分类号： G01R31/28
CPC分类号： G11C29/20 , G01R31/318516
摘要： A semiconductor integrated circuit device having a test circuit including a plurality of gate cells (2) arranged in a matrix; wiring for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires (3) provided along the gate cells in a row direction, each of the gate cells (2) being operatively connected to a row selection wire (3) a plurality of a column read-out wires (4) provided along the gate cells in a column direction, outputs of each of the gate cells (2) being operatively connected to column read-out wires (4), a row selection ring counter (6), operatively connected to the row selection wires (3), for selecting any of the row selection wires (3) and for the selecting of any of the gate cells (2) connected to the selected row selection wire (3); and a data selector (8) and ring counter (7) for reading out of the gate cells (2) arranged in the logic circuits through the column read-out wires (4). Figure 1.
摘要翻译：一种具有测试电路的半导体集成电路器件，包括以矩阵排列的多个栅极单元（2）; 用于连接门单元以构成逻辑电路的布线; 沿着所述栅电池沿行方向设置的多个行选择布线（3），每个栅极单元（2）可操作地连接到行选择布线（3），多个列读出布线（4）沿着列方向沿着栅极单元提供，每个栅极单元（2）的输出可操作地连接到列读出布线（4），行选择环计数器（6），可操作地连接到行选择布线 3），用于选择行选择线（3）中的任何一个，以及用于选择连接到所选择的行选择线（3）的任何门单元（2）; 以及数据选择器（8）和环形计数器（7），用于通过列读出线（4）读出布置在逻辑电路中的门单元（2）。

10. 发明公开

EP0031638A3 A logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：EP0031638A3
公开(公告)日：1981-10-21
申请号：EP80303960
申请日：1980-11-06
申请人： FUJITSU LIMITED
发明人： Sugihara, Takanori , Yoshida, Makoto
IPC分类号： H03K13/258 , H03K23/26 , H03K19/20
CPC分类号： H03K23/54 , G11C19/00
摘要： The logic circuit has cascade-connected flip-flops A, B, C and D. The data inputs D A , Da, Dc and D D to the flip-flops have gate arrangements G A , G B , Gc and G D connected to them. The circuit receives either a shift signal SHT or a count signal CNT. When the shift signal SHT is received the gate arrangements function so that serial input data Sin is fed through and to the flip-flops A, B, C and D in the manner of a shift register. When the count signal CNT is received the gate arrangements function so that the flip-flops A, B, C, D behave as a counter. The same flip-flops A, B, C, D serve for serial-to- parallel conversion of serial input data Sin, counting and parallel-to-serial conversion of a count result.

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