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1. 发明公开

EP0309068A2 Digital data processing system 失效
标题翻译： Digitale Datenverarbeitungsanordnung。
公开(公告)号：EP0309068A2
公开(公告)日：1989-03-29
申请号：EP88202398.9
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Keating, David Lee , Hummel, Mark Douglas , Epstein, David Ira , Normoyle, Kevin B. , Burns, Kenneth , Anderson, Walker , Kimmens, Harold R. , Veres, James Edward , Wallach, Steven Jeffrey
IPC分类号： G06F9/22
CPC分类号： G06F9/268 , G06F9/226 , G06F9/24 , G06F9/264 , G06F12/1027 , G06F2212/2515
摘要： The system comprises processor means (PU 106) for processing the data, a main memory (102) for storing the data and instructions for directing operations of the system, and a bus (MDA 110) for conducting the data and instructions between the memory and the processor means. The processor means comprise a CPU processor (CPUP 122) connected to the bus (MDA 110) for performing arithmetic and logic operations on the data. A microcode processor (IPD 114, US 116) is connected to the bus and is responsive to the instructions and the operations of the system for manipulating and providing sequences of microinstructions for controlling the operations of the system. The microcode processor (IPD 114, US 116) comprises means (IPD 114) connected to the bus (MDA 110) for receiving the instructions, means connected to other portions of the system for receiving information regarding the state of the operations of the system, a microcode memory for storing and providing the sequences of microinstructions, and microcode sequence control means responsive to the received instructions and to the state information for providing addresses to the microcode memory for selecting the sequences of microinstructions.
摘要翻译：该系统包括用于处理数据的处理器装置（PU 106），用于存储用于指导系统操作的数据和指令的主存储器（102），以及用于执行存储器与存储器之间的数据和指令的总线（MDA 110）处理器的手段。处理器装置包括连接到总线（MDA 110）的CPU处理器（CPUP 122），用于对数据进行算术和逻辑运算。微代码处理器（IPD 114，US 116）连接到总线，并且响应于系统的指令和操作，用于操纵和提供用于控制系统操作的微指令序列。微代码处理器（IPD 114，US 116）包括连接到用于接收指令的总线（MDA 110）的装置（IPD 114），连接到系统的其他部分的装置的装置，用于接收关于系统的操作状态的信息，用于存储和提供微指令序列的微代码存储器，以及响应于接收到的指令的微代码序列控制装置和用于向微代码存储器提供地址以选择微指令序列的状态信息。

2. 发明授权

EP0110613B1 Digital data processing system 失效
标题翻译：数字数据处理系统
公开(公告)号：EP0110613B1
公开(公告)日：1991-07-10
申请号：EP83306958.6
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Epstein, David Ira , Keating, David Lee , Normoyle, Kevin B. , Hummel, Mark Douglas , Burns, Kenneth , Anderson, Walker , Veres, James Edward , Kimmens, Harold R. , Wallach, Steven Jeffrey
IPC分类号： G06F12/10
CPC分类号： G06F9/268 , G06F9/226 , G06F9/24 , G06F9/264 , G06F12/1027 , G06F2212/2515

3. 发明公开

EP0309068A3 Digital data processing system 失效
标题翻译：数字数据处理系统
公开(公告)号：EP0309068A3
公开(公告)日：1990-08-16
申请号：EP88202398.9
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Keating, David Lee , Hummel, Mark Douglas , Epstein, David Ira , Normoyle, Kevin B. , Burns, Kenneth , Anderson, Walker , Kimmens, Harold R. , Veres, James Edward , Wallach, Steven Jeffrey
IPC分类号： G06F9/22
CPC分类号： G06F9/268 , G06F9/226 , G06F9/24 , G06F9/264 , G06F12/1027 , G06F2212/2515
摘要： The system comprises processor means (PU 106) for processing the data, a main memory (102) for storing the data and instructions for directing operations of the system, and a bus (MDA 110) for conducting the data and instructions between the memory and the processor means. The processor means comprise a CPU processor (CPUP 122) connected to the bus (MDA 110) for performing arithmetic and logic operations on the data. A microcode processor (IPD 114, US 116) is connected to the bus and is responsive to the instructions and the operations of the system for manipulating and providing sequences of microinstructions for controlling the operations of the system. The microcode processor (IPD 114, US 116) comprises means (IPD 114) connected to the bus (MDA 110) for receiving the instructions, means connected to other portions of the system for receiving information regarding the state of the operations of the system, a microcode memory for storing and providing the sequences of microinstructions, and microcode sequence control means responsive to the received instructions and to the state information for providing addresses to the microcode memory for selecting the sequences of microinstructions.
摘要翻译：该系统包括用于处理数据的处理器装置（PU 106），用于存储数据和用于指导系统操作的指令的主存储器（102），以及用于在存储器和存储器之间执行数据和指令的总线（MDA 110）处理器意味着。处理器装置包括连接到总线（MDA 110）的CPU处理器（CPUP 122），用于对数据执行算术和逻辑运算。微码处理器（IPD114，US116）连接到总线，并且响应系统的指令和操作以操纵和提供用于控制系统操作的微指令序列。微码处理器（IPD 114，US 116）包括连接到总线（MDA 110）用于接收指令的装置（IPD 114），连接到系统的其他部分以接收关于系统操作状态的信息的装置，用于存储和提供微指令序列的微码存储器，以及响应于所接收的指令和用于向微码存储器提供地址以选择微指令序列的状态信息的微码序列控制装置。

4. 发明公开

EP0110613A2 Digital data processing system 失效
标题翻译： Digitale Datenverarbeitungsanordnung。
公开(公告)号：EP0110613A2
公开(公告)日：1984-06-13
申请号：EP83306958.6
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Epstein, David Ira , Keating, David Lee , Normoyle, Kevin B. , Hummel, Mark Douglas , Burns, Kenneth , Anderson, Walker , Veres, James Edward , Kimmens, Harold R. , Wallach, Steven Jeffrey
IPC分类号： G06F12/10
CPC分类号： G06F9/268 , G06F9/226 , G06F9/24 , G06F9/264 , G06F12/1027 , G06F2212/2515
摘要： The system comprises processor means (PU 106) providing addresses to a memory (102) on an address bus (MAD 108). Data and instructions pass between the memory and the processor means by way of a data bus (MDA 110). Within the processing means (PU 106) there is an internal databus (DBUS 112) which provides the data to a central processor (CPUP 122) which performs the arithmetical and logical operations commanded by the user program instructions. The output of the CPU passes to another internal bus (YBUS 124) a memory data buffer (MDB 132) is used to transfer data from the internal databus (DBUS 112) to the main memory and from the main memory to the internal output bus (YBUS 124) connected between the internal buses are a nibble shifter (NIBS 126) and a scratch pad memory (SPAD 128) which provides general scratch pad memory space, general registers for the CPU (122) and space for tables used in transfilming logical addresses to physical memory addresses via a memory address unit (MAD 130). The system operates under microprogram control effected by a control unit (CU 104) including means (IPD 114) prefetching instructions and partially decoding the same and a microsequencer (US 116) which has a permanent store for kernel microcode and a writable memory for further microcode which can be entered via the main memory (102) to adapt the system to a specific instruction set. A memory control unit (MC 118) performs error detection and correction and other memory related operations. Serial input/output (SIO 134) provides communication with a soft console while another unit (DBIO 136) provides communication with bulk memory devices.
摘要翻译：该系统包括向地址总线（MAD108）上的存储器（102）提供地址的处理器装置（PU 106）。数据和指令通过数据总线（MDA 110）在存储器和处理器装置之间传递。在处理装置（PU 106）内有一个内部数据总线（DBUS 112），它将数据提供给执行用户程序指令所指令的算术和逻辑运算的中央处理器（CPUP 122）。 CPU的输出传递到另一个内部总线（YBUS 124），存储器数据缓冲器（MDB 132）用于将数据从内部数据总线（DBUS 112）传送到主存储器，并从主存储器传输到内部输出总线连接在内部总线之间的是三位移位器（NIBS 126）和便携式存储器（SPAD 128），其提供通用暂存器存储器空间，CPU（122）的通用寄存器和用于转换逻辑地址的表的空间通过存储器地址单元（MAD 130）到物理存储器地址。该系统在由包括装置（IPD 114）预取指令和对其进行部分解码的控制单元（CU104））的微程序控制下操作，并且具有用于内核微代码的永久存储器的微定序器（US 116）和用于进一步的微代码的可写存储器其可以经由主存储器（102）输入以使系统适应特定的指令集。存储器控制单元（MC 118）执行错误检测和校正以及其他存储器相关操作。串行输入/输出（SIO 134）提供与软控制台的通信，而另一单元（DBIO 136）提供与大容量存储器设备的通信。

5. 发明公开

EP0312183A3 Digital data processing system 失效
标题翻译：数字数据处理系统
公开(公告)号：EP0312183A3
公开(公告)日：1990-08-16
申请号：EP88202399.7
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Keating, David Lee , Hummel, Mark Douglas , Epstein, David Ira , Normoyle, Kevin B. , Burns, Kenneth , Anderson, Walker , Kimmens, Harold R. , Veres, James Edward , Wallach, Steven Jeffrey
IPC分类号： G06F9/24 , G06F9/22
CPC分类号： G06F9/30145 , G06F9/226 , G06F9/24 , G06F9/264 , G06F9/268 , G06F12/1027 , G06F2212/2515
摘要： The system comprises processor means (PU 106) for processing data, internal memory (102, SPAD 128) for storing data and instructions for directing operations of the system, buses (MDA 110, DBUS 112, YBUS 124) for conducting the data and instructions between the internal memory and the processor means, external terminal means for providing commands for directing the operation of the system, external memory, input/output means (SIO 134, DBIO 136) connected between the terminal means, the external memory means and a bus (DBUS 112, YBUS 124) for conducting the commands and data between the terminal means, the external memory means and the bus means, and microcode control means (CU 104) for providing sequence of microinstructions for controlling the operation of the system. These control means (CU 104) comprise a microsequencer (US 116) which includes a kernel microcode memory responsive to first instructions and commands and permanently storing and providing to the system corresponding first microinstruction sequences, and a writable microcode memory responsive to second instructions and commands and storing and providing to the system corresponding second microinstruction sequences. The external memory stores an initial copy of the second microinstruction sequences, and the first microinstruction sequences including microinstruction sequences for (a) controlling the system to read a second copy of the second microinstruction sequences from the external memory to the internal memory (102, SPAD 128) and (b) to read the second copy of the second microinstruction sequences for the internal memory to the writable microcode memory.
摘要翻译：该系统包括用于处理数据的处理器装置（PU 106），用于存储数据和用于指导系统操作的指令的内部存储器（102，SPAD 128），用于执行数据和指令的总线（MDA 110，DBUS 112，YBUS 124）在内部存储器和处理器装置之间，提供用于指导系统操作的命令的外部终端装置，连接在终端装置，外部存储器装置和总线之间的外部存储器，输入/输出装置（SIO 134，DBIO 136）（DBUS112，YBUS124），用于在终端装置，外部存储器装置和总线装置之间进行命令和数据，微码控制装置（CU104）用于提供用于控制系统操作的微指令序列。这些控制装置（CU 104）包括一个微序列器（US 116），该微序列器包括响应于第一指令和命令并且永久地存储并向系统提供相应的第一微指令序列的内核微码存储器，以及响应于第二指令和命令的可写微码存储器并存储并提供给系统相应的第二微指令序列。外部存储器存储第二微指令序列的初始副本，并且第一微指令序列包括微指令序列，用于（a）控制系统从外部存储器读取第二微指令序列的第二副本到内部存储器（102，SPAD （b）将内部存储器的第二微指令序列的第二副本读到可写微码存储器。

6. 发明公开

EP0312183A2 Digital data processing system 失效
标题翻译： Digitale Datenverarbeitungsanordnung。
公开(公告)号：EP0312183A2
公开(公告)日：1989-04-19
申请号：EP88202399.7
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Keating, David Lee , Hummel, Mark Douglas , Epstein, David Ira , Normoyle, Kevin B. , Burns, Kenneth , Anderson, Walker , Kimmens, Harold R. , Veres, James Edward , Wallach, Steven Jeffrey
IPC分类号： G06F9/24 , G06F9/22
CPC分类号： G06F9/30145 , G06F9/226 , G06F9/24 , G06F9/264 , G06F9/268 , G06F12/1027 , G06F2212/2515
摘要： The system comprises processor means (PU 106) for processing data, internal memory (102, SPAD 128) for storing data and instructions for directing operations of the system, buses (MDA 110, DBUS 112, YBUS 124) for conducting the data and instructions between the internal memory and the processor means, external terminal means for providing commands for directing the operation of the system, external memory, input/output means (SIO 134, DBIO 136) connected between the terminal means, the external memory means and a bus (DBUS 112, YBUS 124) for conducting the commands and data between the terminal means, the external memory means and the bus means, and microcode control means (CU 104) for providing sequence of microinstructions for controlling the operation of the system. These control means (CU 104) comprise a microsequencer (US 116) which includes a kernel microcode memory responsive to first instructions and commands and permanently storing and providing to the system corresponding first microinstruction sequences, and a writable microcode memory responsive to second instructions and commands and storing and providing to the system corresponding second microinstruction sequences. The external memory stores an initial copy of the second microinstruction sequences, and the first microinstruction sequences including microinstruction sequences for (a) controlling the system to read a second copy of the second microinstruction sequences from the external memory to the internal memory (102, SPAD 128) and (b) to read the second copy of the second microinstruction sequences for the internal memory to the writable microcode memory.
摘要翻译：该系统包括用于处理数据的处理器装置（PU 106），用于存储用于指导系统操作的数据和指令的内部存储器（102，SPAD 128），用于执行数据和指令的总线（MDA 110，DBUS 112，YBUS 124）内部存储器和处理器装置之间的外部终端装置，用于提供用于引导系统操作的命令，外部存储器，连接在终端装置，外部存储装置和总线之间的输入/输出装置（SIO134，DBIO136）（DBUS 112，YBUS 124），用于在终端装置，外部存储装置和总线装置之间执行命令和数据;以及微代码控制装置（CU104），用于提供用于控制系统操作的微指令序列。这些控制装置（CU104）包括微定序器（US 116），其包括响应于第一指令和命令的内核微代码存储器，并且永久地存储和提供给系统对应的第一微指令序列，以及响应于第二指令和命令的可写微代码存储器以及向系统存储和提供相应的第二微指令序列。外部存储器存储第二微指令序列的初始副本，并且第一微指令序列包括微指令序列，用于（a）控制系统将第二微指令序列的第二副本从外部存储器读取到内部存储器（102，SPAD 128）和（b）将内部存储器的第二微指令序列的第二副本读入可写入微代码存储器。

7. 发明公开

EP0110613A3 Digital data processing system 失效
标题翻译：数字数据处理系统
公开(公告)号：EP0110613A3
公开(公告)日：1987-01-21
申请号：EP83306958
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Epstein, David Ira , Keating, David Lee , Normoyle, Kevin B. , Hummel, Mark Douglas , Burns, Kenneth , Anderson, Walker , Veres, James Edward , Kimmens, Harold R. , Wallach, Steven Jeffrey
IPC分类号： G11C09/06
CPC分类号： G06F9/268 , G06F9/226 , G06F9/24 , G06F9/264 , G06F12/1027 , G06F2212/2515
摘要： The system comprises processor means (PU 106) providing addresses to a memory (102) on an address bus (MAD 108). Data and instructions pass between the memory and the processor means by way of a data bus (MDA 110). Within the processing means (PU 106) there is an internal databus (DBUS 112) which provides the data to a central processor (CPUP 122) which performs the arithmetical and logical operations commanded by the user program instructions. The output of the CPU passes to another internal bus (YBUS 124) a memory data buffer (MDB 132) is used to transfer data from the internal databus (DBUS 112) to the main memory and from the main memory to the internal output bus (YBUS 124) connected between the internal buses are a nibble shifter (NIBS 126) and a scratch pad memory (SPAD 128) which provides general scratch pad memory space, general registers for the CPU (122) and space for tables used in transfilming logical addresses to physical memory addresses via a memory address unit (MAD 130). The system operates under microprogram control effected by a control unit (CU 104) including means (IPD 114) prefetching instructions and partially decoding the same and a microsequencer (US 116) which has a permanent store for kernel microcode and a writable memory for further microcode which can be entered via the main memory (102) to adapt the system to a specific instruction set. A memory control unit (MC 118) performs error detection and correction and other memory related operations. Serial input/output (SIO 134) provides communication with a soft console while another unit (DBIO 136) provides communication with bulk memory devices.

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