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1. 发明公开

EP4006730A1 PROCÉDÉ DE SIMULATION PARALLÈLE REPRODUCTIBLE DE NIVEAU SYSTÈME ÉLECTRONIQUE MIS EN OEUVRE AU MOYEN D'UN SYSTÈME INFORMATIQUE MULTI-COEURS DE SIMULATION À ÉVÈNEMENTS DISCRETS 审中-公开
公开(公告)号：EP4006730A1
公开(公告)日：2022-06-01
申请号：EP21206831.6
申请日：2021-11-08
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives , Centre National de la Recherche Scientifique - CNRS , Université Claude Bernard Lyon I , ENS - Ecole Normale Supérieure de Lyon
发明人： MOY, Matthieu , SASSOLAS, Tanguy ,
IPC分类号： G06F9/52
摘要： Procédé de simulation a événements discrets parallèle reproductible de niveau système électronique mis en oeuvre au moyen d'un système informatique multi-coeurs, ledit procédé de simulation comprenant une succession de phases d'évaluation, mises en oeuvre par un noyau de simulation exécuté par ledit système informatique, comprenant les étapes suivantes :
- ordonnancement parallèle de processus (1) ;
- detection dynamique d'adresses partagées (2);
- évitement de conflits d'accès (3) a des adresses de la mémoire partagée;
- verification de conflits d'accès (4) a des adresses de mémoire partagée;
- retour en arrière (5), lors d'une detection d'au moins un conflit ; et
- génération d'une trace d'execution (6) permettant la reproduction ultérieure de la simulation a l'identique.

2. 发明公开

EP3129874A1 SYSTEME DE CALCUL DISTRIBUE METTANT EN OEUVRE UNE MEMOIRE TRANSACTIONNELLE MATERIELLE DE TYPE NON-SPECULATIF ET SON PROCEDE D'UTILISATION POUR LE CALCUL DISTRIBUE 有权
标题翻译：系统对于实施非投机性交易ELLEN硬件内存和欲使用的分布式计算分布式计算
公开(公告)号：EP3129874A1
公开(公告)日：2017-02-15
申请号：EP15716477.3
申请日：2015-04-09
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： PEETERS, Julien , VENTROUX, Nicolas , SASSOLAS, Tanguy , SHAPIRO, Marc
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/067 , G06F9/467 , G06F9/528 , G06F13/1663
摘要： The invention relates to a distributed computing system comprising a plurality of processing units (UC) and a shared memory (MP) shared among said processing units, characterised in that it includes at least one hardware module for detecting access conflicts (INSP) of said processing units to said shared memory; said or each one of said conflict-detection hardware modules being configured such as to: store at least one probabilistic data structure, indicating all the addresses of said shared memory involved in all the current transactions; receiving at least one message indicating an access request, by one so-called arithmetic unit, to at least one address of said shared memory; determining, from said probabilistic data structure, whether said address is already involved in a current transaction, and transmitting to said processing unit a message indicating the presence or absence of access conflicts; receiving at least one message indicating or confirming a reservation or a release of at least one such address of said shared memory, and updating said probabilistic data structure so that the reserved addresses and the released addresses are considered, respectively, as being involved/not involved in a current transaction. The invention also relates to a method for using such a system.
摘要翻译：一种分布式计算系统，包括计算单元和存储器计算单元之间共享，并且包括一个硬件模块，用于检测的计算单元对共享存储器访问的冲突; 用于检测配置成冲突各硬件模块：存储概率数据结构，表示在当前的事务参与共享存储器的地址; 通过一个计算单元接收指示请求访问至少一个消息，以在共享存储器的地址; 确定性矿，从概率数据结构，无论地址已经参与了当前事务，并发送一条消息，表明访问冲突的存在或不存在; 接收消息指示或预约的验证性或共享存储器的地址的释放，并更新概率数据结构的保留的地址并释放到被认为是地址，如存在/不被在当前事务参与。提供了一种用于使用该系统的方法。

3. 发明授权

EP3371719B1 PROCEDE DE SIMULATION PARALLELE DE NIVEAU SYSTEME ELECTRONIQUE AVEC DETECTION DES CONFLITS D'ACCES A UNE MEMOIRE PARTAGEE 有权
公开(公告)号：EP3371719B1
公开(公告)日：2019-07-17
申请号：EP16793789.5
申请日：2016-10-26
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： VENTROUX, Nicolas , SASSOLAS, Tanguy
IPC分类号： G06F17/50 , G06F9/52

4. 发明公开

EP3371719A1 PROCEDE DE SIMULATION PARALLELE DE NIVEAU SYSTEME ELECTRONIQUE AVEC DETECTION DES CONFLITS D'ACCES A UNE MEMOIRE PARTAGEE 审中-公开
公开(公告)号：EP3371719A1
公开(公告)日：2018-09-12
申请号：EP16793789.5
申请日：2016-10-26
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： VENTROUX, Nicolas , SASSOLAS, Tanguy
IPC分类号： G06F17/50 , G06F9/52
CPC分类号： G06F17/5022 , G06F9/524
摘要： The invention relates to an electronic system level parallel simulation method carried out by means of a multi-core computer system, comprising the parallel evaluation of a plurality of concurrent processes of said simulation on a plurality of cores of said computer system and comprising a sub-method for detecting conflicts of access to a shared memory of a simulated electronic system, said sub-method being implemented by a simulation core, run by said computer system, and comprising: a step of constructing an oriented graph representing access to said shared memory by the processes evaluated by said concurrent processes; and a step of detecting loops in said graph; a loop being considered representative of a conflict of access to said shared memory. The invention also relates to a computer program product for implementing such a method.

5. 发明授权

EP2956874B1 DISPOSITIF ET PROCÉDÉ POUR ACCÉLÉRER LA PHASE DE MISE À JOUR D'UN NOYAU DE SIMULATION 有权
标题翻译：装置和方法用于加速模拟核心的最后阶段
公开(公告)号：EP2956874B1
公开(公告)日：2017-03-15
申请号：EP14704106.5
申请日：2014-02-05
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： VENTROUX, Nicolas , SASSOLAS, Tanguy
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G01J3/0224 , G02B27/286 , G06F17/5022

7. 发明公开

EP2956874A2 DISPOSITIF ET PROCÉDÉ POUR ACCÉLÉRER LA PHASE DE MISE À JOUR D'UN NOYAU DE SIMULATION 有权
标题翻译： VORRICHTUNG UND VERFAHREN ZUR BESCHLEUNIGUNG DER AKTUALISIERUNGSPHASE EINES SIMULATIONSKERNS
公开(公告)号：EP2956874A2
公开(公告)日：2015-12-23
申请号：EP14704106.5
申请日：2014-02-05
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： VENTROUX, Nicolas , SASSOLAS, Tanguy
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G01J3/0224 , G02B27/286 , G06F17/5022
摘要： The invention proposes a method for accelerating the updating of the connecting elements in a simulation of a system generated in a given hardware description language, the method comprising a phase of evaluating the eligible processes of the system, the evaluation phase comprising write accesses (500) or read accesses to connecting elements. Two write memory locations are provided for each connecting element. The evaluation phase comprises updating a connecting element for each write access or read access to the connecting element. The update phase comprises the following steps: - receiving a selection word associated with the connecting element (501); - selecting one of the two write locations associated with the connecting element on the basis of the value of the selection word received for the connecting element; and - updating the current value of the connecting element from the selected write memory location (503, 505).
摘要翻译：一种用于在根据给定硬件描述语言生成的系统的仿真中加速链接元素的更新的方法，所述方法包括用于评估系统的合格处理的阶段，评估阶段包括对连接元素的写入或读取访问。对于每个链接元素，提供两个写入存储器位置。评估阶段包括更新连接元件的每个写入或读取访问的链接元素。该更新包括以下步骤：接收与链接元素相关联的选择词; 根据为链接元素接收的选择字的值，选择与链接元素相关联的两个写入位置之一; 并且基于所选择的写入存储器位置来更新链接元素的当前值。

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