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1. 发明公开

EP1192712A1 OFFSET AND NON-LINEARITY COMPENSATED AMPLIFIER AND METHOD 有权
标题翻译：失调和NICHTLINEARITÄTKOMPENSIERTERVERSTÄRKER和方法
公开(公告)号：EP1192712A1
公开(公告)日：2002-04-03
申请号：EP00923499.8
申请日：2000-04-19
申请人： Burr-Brown Corporation
发明人： WANG, Binan
IPC分类号： H03F3/14
CPC分类号： H03F3/45479 , H03F2200/261 , H03F2200/331
摘要： Circuitry in an amplifier (1) provides both auto-zeroing of offset errors and finite gain compensation. The circuitry includes a differential main amplifier (3) and a differential auxiliary amplifier (13). During a first phase (ζ1), a previously sampled input voltage is amplified by the main amplifier to produce an output voltage on a first capacitor (C3). A stored prior offset correction voltage stored on a second capacitor (C4A) is applied between the inputs of the auxiliary amplifier, an output of which is coupled to an auxiliary input of the main amplifier to auto-zero its offset voltage. During a second phase (ζ2) the inputs of the main amplifier are short-circuited together, causing it to produce a voltage change on one terminal of the first capacitor (C3), the other terminal of which is switched from ground to one terminal of a second capacitor (C4). This stores updated offset correction voltage on the second capacitor (C4). Since the previous output voltage of the main amplifier remains stored on the first capacitor (C3) during the second phase, the auto-zeroing correction is referenced to the previous value of the output voltage, resulting in compensation for distortion caused by non-linearity of the main amplifier.

2. 发明授权

EP1157494B1 FREQUENCY-SHAPED PSEUDO-RANDOM CHOPPER STABILIZATION CIRCUIT AND METHOD FOR DELTA-SIGMA MODULATOR 有权
标题翻译：用于DELTA-SIGMA调制器的频率形伪随机斩波稳定电路和方法
公开(公告)号：EP1157494B1
公开(公告)日：2004-04-28
申请号：EP00911762.3
申请日：2000-02-10
申请人： Burr-Brown Corporation
发明人： WANG, Binan
IPC分类号： H04K1/00 , H04L7/00 , H04B14/06 , H03M3/02
CPC分类号： H03M3/34 , H03M3/332 , H03M3/43 , H03M3/438
摘要： A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback (18) is applied to a second input of the first adder and a first input of a second adder (16). A 1-bit quantization signal ( phi CH) is produced as an MSB of an output of the first adder and applied to an LSB of a second input of the second adder (16). An error signal (16A) representing the difference between the quantization signal ( phi CH) and the error feedback signal (18) is produced by the second adder (16) and delayed by a predetermined amount to produce the error feedback signal (18), wherein energy of the quantization signal ( phi CH) is spread over a broad frequency spectrum between DC and FS/2. The chopping signals are applied to corresponding chopper switches and used to reduce sensitivity of the delta-sigma modulator.
摘要翻译：用于降低集成电路斩波稳定放大器对互调的灵敏度的系统将伪随机序列信号（11A）施加到第一加法器的第一输入的LSB。错误反馈（18）被施加到第一加法器的第二输入端和第二加法器（16）的第一输入端。产生1位量化信号（φCH）作为第一加法器的输出的MSB并施加到第二加法器（16）的第二输入的LSB。表示量化信号（φCH）和误差反馈信号（18）之间差值的误差信号（16A）由第二加法器（16）产生并被延迟预定量以产生误差反馈信号（18），其中量化信号（φCH）的能量分布在DC和FS / 2之间的宽频谱上。斩波信号被施加到相应的斩波器开关并用于降低Δ-Σ调制器的灵敏度。

3. 发明公开

EP1157494A1 FREQUENCY-SHAPED PSEUDO-RANDOM CHOPPER STABILIZATION CIRCUIT AND METHOD FOR DELTA-SIGMA MODULATOR 有权
标题翻译：带有频率伪任意形状的斩波稳定电路
公开(公告)号：EP1157494A1
公开(公告)日：2001-11-28
申请号：EP00911762.3
申请日：2000-02-10
申请人： Burr-Brown Corporation
发明人： WANG, Binan
IPC分类号： H04K1/00 , H04L7/00 , H04B14/06
CPC分类号： H03M3/34 , H03M3/332 , H03M3/43 , H03M3/438
摘要： A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback (18) is applied to a second input of the first adder and a first input of a second adder (16). A 1-bit quantization signal (ζCH) is produced as an MSB of an output of the first adder and applied to an LSB of a second input of the second adder (16). An error signal (16A) representing the difference between the quantization signal (ζCH) and the error feedback signal (18) is produced by the second adder (16) and delayed by a predetermined amount to produce the error feedback signal (18), wherein energy of the quantization signal (ζCH) is spread over a broad frequency spectrum between DC and FS/2. The chopping signals are applied to corresponding chopper switches and used to reduce sensitivity of the delta-sigma modulator.

4. 发明授权

EP1192712B1 OFFSET AND NON-LINEARITY COMPENSATED AMPLIFIER AND METHOD 有权
标题翻译：偏移和非线性补偿放大器和方法
公开(公告)号：EP1192712B1
公开(公告)日：2007-12-12
申请号：EP00923499.8
申请日：2000-04-19
申请人： Burr-Brown Corporation
发明人： WANG, Binan
IPC分类号： H03F3/14 , H03F1/30 , H03F3/00 , H03F3/45
CPC分类号： H03F3/45479 , H03F2200/261 , H03F2200/331
摘要： Circuitry in an amplifier (1) provides both auto-zeroing of offset errors and finite gain compensation. The circuitry includes a differential main amplifier (3) and a differential auxiliary amplifier (13). During a first phase (ζ1), a previously sampled input voltage is amplified by the main amplifier to produce an output voltage on a first capacitor (C3). A stored prior offset correction voltage stored on a second capacitor (C4A) is applied between the inputs of the auxiliary amplifier, an output of which is coupled to an auxiliary input of the main amplifier to auto-zero its offset voltage. During a second phase (ζ2) the inputs of the main amplifier are short-circuited together, causing it to produce a voltage change on one terminal of the first capacitor (C3), the other terminal of which is switched from ground to one terminal of a second capacitor (C4). This stores updated offset correction voltage on the second capacitor (C4). Since the previous output voltage of the main amplifier remains stored on the first capacitor (C3) during the second phase, the auto-zeroing correction is referenced to the previous value of the output voltage, resulting in compensation for distortion caused by non-linearity of the main amplifier.
摘要翻译：放大器（1）中的电路同时提供失调误差的自动归零和有限增益补偿。该电路包括差分主放大器（3）和差分辅助放大器（13）。在第一阶段（ζ1）期间，先前采样的输入电压被主放大器放大以在第一电容器（C3）上产生输出电压。存储在第二电容器（C4A）上的先前存储的偏移校正电压被施加在辅助放大器的输入端之间，辅助放大器的输出端耦合到主放大器的辅助输入端以自动调零其偏移电压。在第二阶段（ζ2）期间，主放大器的输入端一起短路，使其在第一电容器（C3）的一个端子上产生电压变化，其另一个端子从地切换到第一电容器第二电容器（C4）。这将更新的偏移校正电压存储在第二电容器（C4）上。由于主放大器的前一个输出电压在第二阶段期间保持存储在第一电容器（C3）上，所以自动调零校正以输出电压的先前值为基准，导致补偿由非线性引起的失真主放大器。

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