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1. 发明公开

EP2784940A1 Voltage-controlled oscillator module and phase-locked loop device including the same 有权
标题翻译： Spannungsgesteuertes Oszillatormodul und Phasenregelkreisvorrichtung damit
公开(公告)号：EP2784940A1
公开(公告)日：2014-10-01
申请号：EP13305382.7
申请日：2013-03-28
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David , Lecuyer, Matthieu
IPC分类号： H03L7/099
CPC分类号： H03L7/00 , H03L7/08 , H03L7/099 , H03L2207/06
摘要： A voltage-controlled oscillator (VCO) module (100) combines a low VCO-gain value with compensation for large frequency drifts. The VCO module comprises a VCO circuit (1) and a time-integrator (2). The VCO circuit is fed with a first frequency tuning voltage (V 1 ) and a second frequency tuning voltage (V 2 ) which is produced by the time-integrator from the first frequency tuning voltage. In preferred embodiments, the time-integrator may be comprised of a transconductor (20) connected in series with a capacitor (29), and the transconductor has a linear operation range with low slope or zero-slope, located between two side ranges with deeper slope.
摘要翻译：压控振荡器（VCO）模块（100）将低VCO增益值与大频率漂移的补偿相结合。 VCO模块包括VCO电路（1）和时间积分器（2）。 VCO电路馈送由第一频率调谐电压由时间积分器产生的第一频率调谐电压（V 1）和第二频率调谐电压（V 2）。在优选实施例中，时间积分器可以包括与电容器（29）串联连接的跨导体（20），并且跨导体具有位于两个侧面范围之间的较低斜率或零斜率的线性运算范围，具有更深的坡。

2. 发明授权

EP2804324B1 Digital phase-locked loop device with automatic frequency range selection 有权
标题翻译：带有自动频率范围选择数字锁相环装置
公开(公告)号：EP2804324B1
公开(公告)日：2015-04-15
申请号：EP13305613.5
申请日：2013-05-15
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David , Charpentier, Sébastien , Lecuyer, Matthieu
IPC分类号： H03L7/099 , H03L7/10
CPC分类号： H03L7/0992 , H03L7/093 , H03L7/099 , H03L7/103 , H03L7/1976 , H03L2207/06

3. 发明公开

EP2806562A1 Programmable frequency divider module with duty cycle close to fifty percent 审中-公开
标题翻译：程式计算机频率计算器快速fünfzigProzent
公开(公告)号：EP2806562A1
公开(公告)日：2014-11-26
申请号：EP13305661.4
申请日：2013-05-22
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David , Gervais, Didier
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/665 , H03K21/026
摘要： A programmable frequency divider module (10) is based on a programmable re-load counter (1) and a digital combination (11) comprising an N-bit adder. In a preferred implementation, a down-count from a division ratio value (R) down to one-value is repeated, and a down-count signal is added to an offset value itself determined as a function of the division ratio value. The adder carry generates a derived clock signal having a frequency equal to that of an initial clock signal divided by the division ratio value. Such frequency divider module produces the derived clock signal with low noise and duty cycle close to 50%. It is well adapted in particular for clocking analog-to-digital converters, digital-to-analog converters and phase-locked loop devices.
摘要翻译：可编程分频器模块（10）基于可编程重载计数器（1）和包括N位加法器的数字组合（11）。在优选的实施方式中，重复从分频比值（R）下降到一值的递减计数，并将递减计数信号添加到作为分频比值的函数确定的偏移值本身。加法器进位产生具有等于初始时钟信号的频率等于分频比的频率的导出时钟信号。这种分频器模块产生低噪声和占空比接近50％的导出时钟信号。它特别适用于时钟模数转换器，数模转换器和锁相环设备。

4. 发明授权

EP2784940B1 Voltage-controlled oscillator module and phase-locked loop device including the same 有权
标题翻译：压控振荡器模块和锁相环装置，从而
公开(公告)号：EP2784940B1
公开(公告)日：2015-03-18
申请号：EP13305382.7
申请日：2013-03-28
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David , Lecuyer, Matthieu
IPC分类号： H03L7/099
CPC分类号： H03L7/00 , H03L7/08 , H03L7/099 , H03L2207/06

5. 发明公开

EP2797235A1 Phase-locked loop device with managed transition to random noise operation mode 有权
标题翻译： Phasenregelkreisvorrichtung mit gesteuertemÜbergangzumWeißrauschen-Betriebsmodus
公开(公告)号：EP2797235A1
公开(公告)日：2014-10-29
申请号：EP13305526.9
申请日：2013-04-22
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David
IPC分类号： H03L7/107
CPC分类号： H03L7/095 , H03L7/1075 , H03L2207/06
摘要： A phase-locked loop device is adapted for managing transition from relaxation-oscillation mode to random noise operation mode. It is designed for progressively reducing proportional (K P ) and integral (K I ) coefficients that are implemented in a loop filter (2) of the PLL device. Recovering of last values formerly used for said proportional and integral coefficients is also provided, in case PLL lock state is lost. Such transition management may be combined with using a voltage-controlled oscillator (3) within the PLL device, which has several control inputs.
摘要翻译：锁相环装置适用于管理从松弛振荡模式到随机噪声运行模式的转变。它被设计用于逐渐减少在PLL器件的环路滤波器（2）中实现的比例（K P）和积分（K I）系数。还提供了以前用于所述比例和积分系数的最后值的恢复，以防PLL锁定状态丢失。这种转换管理可以与使用具有多个控制输入的PLL装置内的压控振荡器（3）组合。

6. 发明授权

EP2797235B1 Phase-locked loop device with managed transition to random noise operation mode 有权
标题翻译：具有受控过渡到白噪声的操作模式锁相环装置
公开(公告)号：EP2797235B1
公开(公告)日：2015-03-18
申请号：EP13305526.9
申请日：2013-04-22
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David
IPC分类号： H03L7/095 , H03L7/107
CPC分类号： H03L7/095 , H03L7/1075 , H03L2207/06

7. 发明公开

EP2804324A1 Digital phase-locked loop device with automatic frequency range selection 有权
标题翻译： Digitale Phasenregelkreisvorrichtung mit automatischer Frequenzbereichsauswahl
公开(公告)号：EP2804324A1
公开(公告)日：2014-11-19
申请号：EP13305613.5
申请日：2013-05-15
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David , Charpentier, Sébastien , Lecuyer, Matthieu
IPC分类号： H03L7/099 , H03L7/10
CPC分类号： H03L7/0992 , H03L7/093 , H03L7/099 , H03L7/103 , H03L7/1976 , H03L2207/06
摘要： A digital phase-locked loop (PLL) device includes a digital loop filter (106) which is provided with both a VCO-loop output and a DCO-loop output. The VCO-loop output is connected to an analog input of a multiband voltage-controlled oscillator (VCO) module (100) for allowing usual operation of the PLL with a direct voltage acting as feedback parameter. The DCO-loop output is connected to a digital control input of the multiband VCO module for allowing automatic frequency range selection. A code value which is produced by the digital loop filter acts as feedback parameter during the frequency range selection. Rapid and precise range selection can thus be performed.
摘要翻译：数字锁相环（PLL）装置包括一个数字环路滤波器（106），它提供VCO环路输出和DCO环路输出。 VCO环路输出连接到多频带压控振荡器（VCO）模块（100）的模拟输入端，用于允许PLL作为反馈参数的直流电压的通常操作。 DCO环路输出连接到多频段VCO模块的数字控制输入，用于允许自动频率范围选择。由数字环路滤波器产生的码值在频率范围选择期间作为反馈参数。因此可以进行快速精确的范围选择。

8. 发明公开

EP2796945A1 Time-to-digital conversion with analog dithering 无效
标题翻译： Zeit-Digital-Umwandlung mit模拟抖动
公开(公告)号：EP2796945A1
公开(公告)日：2014-10-29
申请号：EP13305539.2
申请日：2013-04-24
申请人： Asahi Kasei Microdevices Corporation
发明人： Canard, David , Delorme, Julien
IPC分类号： G04F10/00 , H03M1/50
CPC分类号： H03M1/201 , G04F10/005 , H03L7/085 , H03L7/093 , H03L7/18
摘要： There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.
摘要翻译：描述了使用基于延迟元件的时间 - 数字转换器TDC（20）的布置的时间 - 数字转换方案，其中抖动内置在数字域中并且作为供应的调制被引入模拟域电压（TDC供电）提供TDC的延迟元件，每个延迟元件具有表现出对其电源电压的依赖性的传播延迟。

9. 发明公开

EP2793037A1 Digital frequency meter 审中-公开
标题翻译：数码频道
公开(公告)号：EP2793037A1
公开(公告)日：2014-10-22
申请号：EP13305500.4
申请日：2013-04-17
申请人： Asahi Kasei Microdevices Corporation
发明人： Charpentier, Sébastien , Canard, David
IPC分类号： G01R23/02 , G01R31/28 , H03L7/02 , H03L7/18
CPC分类号： G01R23/02 , G01R31/2824 , H03L7/02 , H03L7/093 , H03L7/1976
摘要： A digital frequency meter comprises a clock comparator (1), a loop filter (2) and a frequency converter (3) connected so as to form a closed-loop system. The loop filter is of proportional-integral type and outputs a digital signal which is used as division factor within the frequency converter. The frequency measurement result is based on said digital signal. Such digital frequency meter can be obtained by re-wiring components pertaining to a phase-locked loop (PLL) device, and may be used for testing a voltage-controlled oscillator of the PLL device itself.
摘要翻译：数字频率计包括时钟比较器（1），环路滤波器（2）和频率转换器（3），以形成闭环系统。环路滤波器具有比例积分型，并输出用作变频器内分频系数的数字信号。频率测量结果基于所述数字信号。这种数字频率计可以通过重新布线有关锁相环（PLL）装置的组件来获得，并且可以用于测试PLL装置本身的压控振荡器。

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