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1. 发明公开

EP0914660A4 SEMICONDUCTOR MEMORY FOR SECURE DATA STORAGE 失效
标题翻译：半导体存储器安全数据存储
公开(公告)号：EP0914660A4
公开(公告)日：2005-01-12
申请号：EP98918655
申请日：1998-04-24
申请人： ATMEL CORP
发明人： PATHAK SAROJ , PATHAK JAGDISH
IPC分类号： G11C16/06 , G11C16/22 , G11C16/28 , G11C7/06
CPC分类号： G11C16/22 , G11C16/28
摘要： A memory device includes a memory cell (102) whose data state is sensed by a sense amplifier (100). A balance amplifier (200) having the same construction as the sense amplifier is utilized to sense a balance cell (202) having the same construction as the memory cell. The balance cell is maintained in a erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit (208) is used to adjust the conductivity of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.

2. 发明公开

EP0960421A4 BITLINE LOAD AND PRECHARGE STRUCTURE FOR AN SRAM MEMORY 失效
标题翻译： LADUNGS-UND VORLADUNGSBITLEITUNGSSTRUKTUR EINES SRAM-SPEICHERS
公开(公告)号：EP0960421A4
公开(公告)日：2003-07-09
申请号：EP98903387
申请日：1998-01-06
申请人： ATMEL CORP
发明人： PATHAK SAROJ , PAYNE JAMES E
IPC分类号： G11C11/41 , G11C11/419
CPC分类号： G11C11/419
摘要： An SRAM (Figs 6 and 7) monitors its WRITE/READ pin (77), and when the SRAM is in a read mode, initiates a first precharging scheme in which every complementary bitline pair (BL1, BL#1; BL2, BL#2; BL3, BL#3; BLn, BL#n) is directly coupled to Vcc via a first pmos transistor (Ld1, Ld1#; Ld2, Ld2#; Ld3, Ld#3; Ldn, Ldn#) which is permanently turned on, regardless of whether a memory cell is being read or not, and both true and false bitlines in every complementary bitline pair are coupled together via a second pmos transistor (Eq1, Eq2, Eq3, Eqn) as long as the SRAM remains in a read mode. When in a write mode, a second precharging scheme is initiated, causing the second pmos transistor to be turned off and only the first pmos transistors remain active. The termination of the write mode activates a third precharging scheme which causes all the bitlines, both true and false, within the memory array to be momentarily shorted together (S1, S2, Sn-1).
摘要翻译： SRAM（图6和图7）监视其WRITE / READ引脚（77），并且当SRAM处于读取模式时，启动第一预充电方案，其中每个互补位线对（BL1，BL＃1; BL2，BL＃ 2; BL3，BL＃3; BLn，BL＃n）通过第一pmos晶体管（Ld1，Ld1＃; Ld2，Ld2＃; Ld3，Ld＃3; Ldn，Ldn＃）直接耦合到Vcc，不管是否正在读取存储器单元，并且只要SRAM保持在a中，每个互补位线对中的真和假位线都通过第二pmos晶体管（Eq1，Eq2，Eq3，Eqn）耦合在一起读模式。当处于写入模式时，启动第二预充电方案，导致第二pmos晶体管关断，并且只有第一pmos晶体管保持有效。写入模式的终止激活第三预充电方案，其导致存储器阵列内的所有位线（真和假）一起短暂地短路（S1，S2，Sn-1）。

3. 发明公开

EP0693217A4 ZERO POWER HIGH SPEED PROGRAMMABLE CIRCUIT DEVICE ARCHITECTURE 失效转让
标题翻译：低功耗可编程高速电路架构
公开(公告)号：EP0693217A4
公开(公告)日：1998-09-30
申请号：EP95908799
申请日：1995-02-02
申请人： ATMEL CORP
发明人： PATHAK SAROJ , PAYNE JAMES E
IPC分类号： G11C17/00 , G11C14/00 , G11C16/04 , G11C11/34
CPC分类号： G11C14/00
摘要： A non-volatile, low, and zero power, high speed self-sensing programmable device and architecture including a non-volatile self-sensing cell. The non-volatile self-sensing cell is connected out of the speed path of the programmable device, permitting rapid, non-volatile programming and reading operations to be conducted. According to one version, two self-sensing cells are provided with a means for selecting one of the cells for programming or read operation. Each non-volatile self-sensing cell includes a latch having cross-coupled, pull-up transistors and non-volatile pull-down cells. The cross-coupled pull-up transistors are field effect transistors having gates which are connected to the opposite sources of the cross-coupled pull-up transistors.

4. 发明公开

EP1086449A4 CIRCUIT FOR TRANSFERRING HIGH VOLTAGE VIDEO SIGNAL WITHOUT SIGNAL LOSS 审中-公开
标题翻译：电路是否高压视频信号的无信号损失传输
公开(公告)号：EP1086449A4
公开(公告)日：2003-08-27
申请号：EP99925798
申请日：1999-05-25
申请人： ATMEL CORP
发明人： PATHAK SAROJ , PAYNE JAMES E , ROSENDALE GLEN A , HANGZO NIANGLAMCHING
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G3/2074 , G09G3/3677 , G09G2300/0876 , G09G2310/0289
摘要： A circuit (202; 204) for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor (308; 308') powered by a high voltage power source to bias a pass transistor (114; 124) at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor (304; 304') provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor (306; 306') operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.

5. 发明公开

EP1078370A4 SENSE AMPLIFIER WITH ZERO POWER IDLE MODE 审中-公开
标题翻译： LESEVERSTÄRKEROHNE ENERGIEAUFNAHME BEI LEERLAUF
公开(公告)号：EP1078370A4
公开(公告)日：2001-07-04
申请号：EP99914242
申请日：1999-03-29
申请人： ATMEL CORP
发明人： PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
IPC分类号： G11C16/06 , G11C7/06 , G11C7/10 , G11C7/00
CPC分类号： G11C7/062 , G11C7/065 , G11C7/1036
摘要： A sense amplifier (200) for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controlled manner (270), in response to a control pulse (SAEN). The control pulse (SAEN) is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps (200) are utilized to read out in parallel fashion the N memory cells (bits) comprising an accessed memory location. The sense amps (200) are therefore active only of a period of time sufficient to read out a memory cell.
摘要翻译：响应于控制脉冲（SAEN），在串行配置存储器中使用的读出放大器（200）包括以受控方式启用和禁用（270）的多个级。控制脉冲（SAEN）是在外部提供的时钟信号的每N个周期产生的，该时钟用于输出代表存储器装置内容的比特流。在优选实施例中，利用N个这样的读出放大器（200）以并行方式读出包括被访问的存储器位置的N个存储器单元（位）。因此，读出放大器（200）仅在足以读出存储单元的时间段内有效。

6. 发明公开

EP0954864A4 ZERO POWER HIGH SPEED CONFIGURATION MEMORY 有权
标题翻译：性能免费高速内存配置
公开(公告)号：EP0954864A4
公开(公告)日：2001-01-31
申请号：EP98960402
申请日：1998-11-19
申请人： ATMEL CORP
发明人： PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
IPC分类号： G11C16/02 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1039
摘要： A serial configuration memory device (100) comprises an architecture wherein the reading out of data and the outputting (52) of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme (34 and 44) is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

7. 发明公开

EP1034619A4 ZERO POWER POWER-ON-RESET CIRCUIT 有权
标题翻译：性能LOSE快速上电复位电路
公开(公告)号：EP1034619A4
公开(公告)日：2003-09-10
申请号：EP98958071
申请日：1998-11-20
申请人： ATMEL CORP
发明人： PATHAK JAGDISH , PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).

8. 发明公开

EP1123556A4 FUSE CIRCUIT HAVING ZERO POWER DRAW FOR PARTIALLY BLOWN CONDITION 有权
标题翻译： WITH ZERO性能类偏保险丝熔断保险丝电路
公开(公告)号：EP1123556A4
公开(公告)日：2003-09-03
申请号：EP99930292
申请日：1999-06-15
申请人： ATMEL CORP
发明人： PATHAK SAROJ , PAYNE JAMES E
IPC分类号： G11C17/18 , G11C17/16 , G11C29/00 , H01H20060101 , H01H37/76 , H01H85/00 , H01H85/044 , H01H85/46 , H01L21/82 , H01L21/822 , H01L27/00 , H01L27/04 , H03K17/56 , H03K19/003
CPC分类号： G11C17/18
摘要： A fuse circuit (100) includes a fusible element (110) and a feedback path which causes the circuit to behave as if the fusible element (110) is fully blown even though the fusible element (110) in fact is partially intact. While a partially intact fuse normally would result in a continuous drain of power, the feedback path cuts of the current flow through the partially intact fusible element (110).

9. 发明公开

EP0740859A4 ELECTROSTATIC DISCHARGE CIRCUIT FOR HIGH SPEED, HIGH VOLTAGE CIRCUITRY 失效
标题翻译：电气放电电路基础上，高速高压电路
公开(公告)号：EP0740859A4
公开(公告)日：1998-04-22
申请号：EP95906819
申请日：1995-01-10
申请人： ATMEL CORP
发明人： PAYNE JAMES E , PATHAK SAROJ , ROSENDALE GLEN A
IPC分类号： H01L27/088 , H01L21/8234 , H02H7/20 , H02H9/04 , H03K19/003 , H04B15/00 , H03B1/04 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/20 , H02H3/22 , H02H7/00 , H02H9/00 , H03K5/00 , H04B1/10
CPC分类号： H03K19/00315 , H02H9/046
摘要： A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node (30). The first controlled path is from the signal node to (Vcc) via the source and drain electrodes of a first transistor (36). The gate of the transistor is at a soft ground by connection of the gate through a resistor (42) and an inverter (44) to a fixed voltage supply potential (Vcc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second (50) and third (52) transistors to ground. The second transistor (50) has a gate tied at (Vcc) by means of a resistor (62) and an inverter (66) to ground. The third transistor (52) is at soft ground by means of a resistor (64) and inverter (68) to (Vcc). The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor (54), if low voltage circuitry (32) is tied to the signal node (30). The fourth transistor (54) includes a gate that is tied high by connection of the gate to ground via a resistor (82) and inverter (84).

10. 发明公开

EP1547248A4 HIGH SPEED ZERO DC POWER PROGRAMMABLE LOGIC DEVICE (PLD) ARCHITECTURE 审中-公开
标题翻译：架构用于可编程逻辑器件（PLD）高速和ZERO直流电源
公开(公告)号：EP1547248A4
公开(公告)日：2006-08-23
申请号：EP03797833
申请日：2003-08-06
申请人： ATMEL CORP
发明人： PATHAK SAROJ , PAYNE JAMES E , NGUYEN VICTOR V , KUO HARRY H
IPC分类号： G11C16/04 , G11C16/26 , H03K19/177
CPC分类号： H03K19/1776 , G11C16/0433 , G11C16/26 , H03K19/17704 , H03K19/17728 , H03K19/1778 , H03K19/17784
摘要： A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells (Fig.3). Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit (330-333), a settable latch (320-323), a signal path means (360A, 360B), and an output logic gate (350). The signal-path means coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block (402-408) for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) (700) which includes an array of word lines (pwd) and bit lines (vcol, pcol) arranged in rows and columns for addressing, an array of OR gates (740), and a plurality of output logic circuits (750).

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