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1. 发明公开

EP0574184A3 High speed CMOS output buffer circuits 失效
标题翻译：高速CMOS输出缓冲电路
公开(公告)号：EP0574184A3
公开(公告)日：1994-02-23
申请号：EP93304317.6
申请日：1993-06-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00361 , H03K17/163
摘要： An output buffer circuit is disclosed that minimizes signal oscillation or ringing on a data bus while limiting the power dissipated. This circuit includes a pair of reference voltage generators which provide damp voltages that limit the signal oscillation and a mechanism for shutting down the appropriate generator when it is not operating. The output buffer circuit has the capability of driving the output resistors to their CMOS levels in order to maximize the sinking and sourcing currents.
摘要翻译：公开了一种输出缓冲电路，其在数据总线上最小化信号振荡或振铃，同时限制功耗。该电路包括一对参考电压发生器，用于提供限制信号振荡的阻尼电压，以及一个在不工作时关闭合适发生器的机制。输出缓冲电路具有将输出电阻驱动至其CMOS电平的能力，以最大限度地提高灌电流和源电流。

2. 发明公开

EP0533339A2 CMOS output buffer circuits 失效
标题翻译： CMOS-Ausgangspufferschaltungen。
公开(公告)号：EP0533339A2
公开(公告)日：1993-03-24
申请号：EP92307271.4
申请日：1992-08-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Runaldue, Thomas J. , Mahmood, Qazi
IPC分类号： H03K19/0185 , H03K19/003 , H01L27/088
CPC分类号： H03K17/04106 , H01L27/088 , H03K17/162 , H03K19/00315 , H03K19/00361 , H03K2217/0018
摘要： A CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect includes an N-channel pull-up transistor (N2), an N-channel coupling transistor (N1), and an N-channel discharging transistor (N3). The pull-up transistor has its drain connected to an upper power supply potential (VCC), its source connected to an output node (20), its gate connected to a first internal node (B), and its local substrate connected to a second internal node (A). The coupling transistor has its source connected to the second internal node (A), its drain connected to the source of the pull-up transistor, its gate connected to the first internal node (B), and its local substrate connected to the local substrate of the pull-up transistor (N2). The discharging transistor has its drain connected to the second internal node (A), its source connected to a lower power supply potential (VCC), its gate connected to a third internal node (C), and its local substrate connected to the lower power supply potential (VSS). The coupling transistor and the discharging transistor serve to reduce the body effect on the pull-up transistor (N2) and to provide higher immunity from noise on the upper power supply potential (VCC).
摘要翻译：采用具有减小的体效应的N沟道上拉晶体管的CMOS输出缓冲电路包括N沟道上拉晶体管（N2），N沟道耦合晶体管（N1）和N沟道放电晶体管（N3 ）。上拉晶体管的漏极连接到上电源电位（VCC），其源极连接到输出节点（20），其栅极连接到第一内部节点（B），并且其栅极连接到第二内部节点内部节点（A）。耦合晶体管的源极连接到第二内部节点（A），其漏极连接到上拉晶体管的源极，其栅极连接到第一内部节点（B），其局部衬底连接到局部衬底的上拉晶体管（N2）。放电晶体管的漏极连接到第二内部节点（A），其源极连接到较低的电源电位（VCC），其栅极连接到第三内部节点（C），其局部衬底连接到较低功率供电电位（VSS）。耦合晶体管和放电晶体管用于减小上拉晶体管（N2）的体效应，并提供较高的上电源电压（VCC）上的噪声抗扰度。

3. 发明授权

EP0574168B1 High speed CMOS bus driver circuits 失效
标题翻译：快速CMOS总线驱动器电路
公开(公告)号：EP0574168B1
公开(公告)日：1997-07-16
申请号：EP93304166.7
申请日：1993-05-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003
CPC分类号： H03K19/00361

4. 发明公开

EP0574168A3 High speed CMOS bus driver circuits 失效
标题翻译：高速CMOS总线驱动器电路
公开(公告)号：EP0574168A3
公开(公告)日：1994-02-02
申请号：EP93304166.7
申请日：1993-05-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： A high speed bus driver circuit is disclosed that minimizes output signal oscillation by maintaining the clamp voltage at specified levels. The driver circuit includes a pair of voltage preference circuits that are designed to deliver the appropriate clamp voltages even at the best case speed corners, the circuit prevents simultaneous turn on of drive transistors, equalizes the propagation delay and provides for first access for tri-stating the bus driver transistors.
摘要翻译：公开了一种高速总线驱动器电路，其通过将钳位电压维持在特定的电平来使输出信号振荡最小化。该驱动器电路包括一对电压优先电路，该电路被设计为即使在最佳情况下的速度拐角也提供适当的钳位电压，该电路防止驱动晶体管的同时导通，均衡传播延迟并提供三态总线驱动器晶体管。

5. 发明公开

EP0574184A2 High speed CMOS output buffer circuits 失效
标题翻译： Schnelle CMOS Ausgangspufferschaltungen。
公开(公告)号：EP0574184A2
公开(公告)日：1993-12-15
申请号：EP93304317.6
申请日：1993-06-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00361 , H03K17/163
摘要： An output buffer circuit is disclosed that minimizes signal oscillation or ringing on a data bus while limiting the power dissipated. This circuit includes a pair of reference voltage generators which provide damp voltages that limit the signal oscillation and a mechanism for shutting down the appropriate generator when it is not operating. The output buffer circuit has the capability of driving the output resistors to their CMOS levels in order to maximize the sinking and sourcing currents.
摘要翻译：公开了一种输出缓冲器电路，其最小化数据总线上的信号振荡或振铃，同时限制功耗。该电路包括一对参考电压发生器，其提供限制信号振荡的阻尼电压，以及用于当其不工作时关闭适当发电机的机构。输出缓冲电路具有将输出电阻驱动到其CMOS电平的能力，以便最大限度地减小和吸收电流。

6. 发明授权

EP0574184B1 High speed CMOS output buffer circuits 失效
标题翻译：快速CMOS输出缓冲器电路
公开(公告)号：EP0574184B1
公开(公告)日：1997-08-13
申请号：EP93304317.6
申请日：1993-06-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00361 , H03K17/163

7. 发明公开

EP0533339A3 CMOS output buffer circuits 失效
标题翻译： CMOS输出缓冲电路
公开(公告)号：EP0533339A3
公开(公告)日：1995-02-08
申请号：EP92307271.4
申请日：1992-08-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Runaldue, Thomas J. , Mahmood, Qazi
IPC分类号： H03K19/0185 , H03K19/003 , H01L27/088
CPC分类号： H03K17/04106 , H01L27/088 , H03K17/162 , H03K19/00315 , H03K19/00361 , H03K2217/0018
摘要： A CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect includes an N-channel pull-up transistor (N2), an N-channel coupling transistor (N1), and an N-channel discharging transistor (N3). The pull-up transistor has its drain connected to an upper power supply potential (VCC), its source connected to an output node (20), its gate connected to a first internal node (B), and its local substrate connected to a second internal node (A). The coupling transistor has its source connected to the second internal node (A), its drain connected to the source of the pull-up transistor, its gate connected to the first internal node (B), and its local substrate connected to the local substrate of the pull-up transistor (N2). The discharging transistor has its drain connected to the second internal node (A), its source connected to a lower power supply potential (VCC), its gate connected to a third internal node (C), and its local substrate connected to the lower power supply potential (VSS). The coupling transistor and the discharging transistor serve to reduce the body effect on the pull-up transistor (N2) and to provide higher immunity from noise on the upper power supply potential (VCC).
摘要翻译：采用体效应降低的N沟道上拉晶体管的CMOS输出缓冲电路包括N沟道上拉晶体管（N 2），N沟道耦合晶体管（N 1）和N沟道放电晶体管（N 3 ）。上拉晶体管的漏极连接到高电源电位（VCC），其源极连接到输出节点（20），其栅极连接到第一内部节点（B），并且其局部衬底连接到第二内部节点（A）。耦合晶体管的源极连接到第二内部节点（A），其漏极连接到上拉晶体管的源极，其栅极连接到第一内部节点（B），并且其局部衬底连接到局部衬底的上拉晶体管（N2）。放电晶体管的漏极连接至第二内部节点（A），其源极连接至较低电源电位（VCC），其栅极连接至第三内部节点（C），并且其局部衬底连接至较低电源供应潜力（VSS）。耦合晶体管和放电晶体管用于减小对上拉晶体管（N2）的本体效应，并且对较高电源电位（VCC）提供较高的抗噪声免疫力。

8. 发明公开

EP0574168A2 High speed CMOS bus driver circuits 失效
标题翻译： Schnelle CMOS Bustreiberschaltungen。
公开(公告)号：EP0574168A2
公开(公告)日：1993-12-15
申请号：EP93304166.7
申请日：1993-05-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： A high speed bus driver circuit is disclosed that minimizes output signal oscillation by maintaining the clamp voltage at specified levels. The driver circuit includes a pair of voltage preference circuits that are designed to deliver the appropriate clamp voltages even at the best case speed corners, the circuit prevents simultaneous turn on of drive transistors, equalizes the propagation delay and provides for first access for tri-stating the bus driver transistors.
摘要翻译：公开了一种高速总线驱动器电路，其通过将钳位电压维持在指定电平来使输出信号振荡最小化。驱动器电路包括一对电压偏好电路（102,104），其被设计成即使在最佳情况下的转速拐角处也传递适当的钳位电压，该电路可防止驱动晶体管（MP1，MN1）同时导通，使传播延迟和提供三通道总线驱动晶体管的第一次访问。

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