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    • 8. 发明公开
    • MULTILEVEL CONVERTER
    • 多级转换器
    • EP3114763A1
    • 2017-01-11
    • EP14707805.9
    • 2014-03-05
    • ABB Schweiz AG
    • LACHICHI, AmelDIJKHUIZEN, FransHYTTINEN, MatsNAWAZ, MuhammadCHEN, Nan
    • H02M7/00H02M7/48H02M7/483
    • H02M7/003H02M7/48H02M2007/4835
    • A multilevel converter cell or power electronics building block (4a, 4b, 4c, 4d) for a multilevel converter comprising a half bridge module (6, 6') having a capacitor unit (8, 8') and at least two semiconductor switches (24, 24', 24'', 24'''), a gate unit (12, 12') configured to control the semiconductor switches, an electric conductor (32), at least a first and second terminal portions (33a, 33b) and a sub cell (5, 5a, 5b, 5a', 5b'). The sub cell (5, 5a, 5b, 5a', 5b') may comprise at least two half bridge modules connected in parallel and the electric conductor and the two terminal portions (33a, 33b) are configured to be connected to the sub cell in at least two different ways in order to provide a half bridge configured sub cell (5a, 5a') or a full bridge configured sub cell (5b, 5b') for the multilevel converter cell.
    • 一种用于多电平转换器的多电平转换器单元或功率电子构件块(4a,4b,4c,4d),包括具有电容器单元(8,8')的半桥模块(6,6')和至少两个半导体开关 ,用于控制半导体开关的门单元(12,12'),电导体(32),至少第一和第二端子部分(33a,33b,24,24',24“,24” )和子单元(5,5a,5b,5a',5b')。 子电池(5,5a,5b,5a',5b')可以包括至少两个并联连接的半桥模块,并且电导体和两个端子部分(33a,33b)被配置为连接到子电池 以至少两种不同的方式,以便为多电平转换器单元提供半桥配置的子电池(5a,5a')或全桥配置的子电池(5b,5b')。
    • 10. 发明公开
    • BACK-TO-BACK CONVERTER ARRANGEMENT
    • EP3734827A1
    • 2020-11-04
    • EP20172277.4
    • 2020-04-30
    • ABB Schweiz AG
    • OKAZAKI, YuheiDIJKHUIZEN, Frans
    • H02M7/219H02M7/483
    • An MMC of a back-to-back converter arrangement comprises a first and a second phase leg connected between a first DC terminal having a first DC voltage and a second DC terminal having a second DC voltage, the phase legs comprising upper and lower arms with submodules, where each submodule comprises an energy storage element and the junction between two arms provides a corresponding AC terminal. Each phase leg is controlled (42) according to a scheme for generating a waveform on the corresponding AC terminal, which control comprises controlling (42a) the upper phase arm to bypass their energy storage elements and the lower phase arm to be blocked in a first interval (TI1), controlling (42b) the upper and lower phase arms to transition from the first to the second DC voltage in a second interval (TI2), controlling (42c) the upper phase arm to be blocked and the lower phase arm to bypass their energy storage elements in a third interval (TI3), and controlling (42d) the upper and lower phase arms to transition from the second to the first DC voltage in a fourth interval (TI4).