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1. 发明公开

EP4070431A1 INTEGRATION OF BATTERIES AND SUPER-CAPACITORS IN A VEHICULAR POWER SUPPLY SYSTEM 审中-公开
公开(公告)号：EP4070431A1
公开(公告)日：2022-10-12
申请号：EP19816663.9
申请日：2019-12-05
申请人： ABB Schweiz AG
发明人： ABDELHAKIM, Ahmed , DIJKHUIZEN, Frans
IPC分类号： H02J7/00 , H02J7/34

2. 发明公开

EP4022732A1 RESTORATION OF FAULT INSULATED FEEDER 审中-公开
公开(公告)号：EP4022732A1
公开(公告)日：2022-07-06
申请号：EP19761821.8
申请日：2019-08-28
申请人： ABB Schweiz AG
发明人： MAJUMDER, Ritwik , BERGGREN, Bertil , SCHAEFFER, David , ZHANG, Lidong , DIJKHUIZEN, Frans
IPC分类号： H02J3/08 , H02J3/36 , H02J3/00 , H02H3/06 , H02H7/28

3. 发明公开

EP3633816A1 INVERTER ARRANGEMENT EMPLOYING PHOTOVOLTAIC ENERGY DELIVERY ELEMENTS 审中-公开
公开(公告)号：EP3633816A1
公开(公告)日：2020-04-08
申请号：EP18197993.1
申请日：2018-10-01
申请人： ABB Schweiz AG
发明人： DA SILVEIRA POSTIGLIONE, Cicero , DIJKHUIZEN, Frans , SVENSSON, Jan , NAMI, Alireza , CANALES, Francisco
IPC分类号： H02J3/38 , H02M7/483 , H02M7/487
摘要： An inverter arrangement (10A) based on photovoltaic elements comprises at least two strings comprising switching elements, which strings are connected to at least two AC terminals (AC1, AC2, AC3), where at least one of the strings is a string of submodules (SiA, S2A, S3A, S4A, S5A, S6A, S1B, S2B, S3B, S4B, S5B, S6B, S1C, S2C, S3C, S4C, S5C, S6C), each submodule comprising at least two switching elements and an energy storage element, having DC terminals and being configured to make a voltage contribution to the forming of an AC voltage on an AC terminal, and a number of input stages (IS1, IS2, IS3, IS4, IS5, IS6) each comprising at least one energy delivery element, where at least some of the energy delivery elements are photovoltaic elements, each input stage being connected to DC terminals of a corresponding for delivering power to or from at least one AC terminal (AC1, AC2, AC3) when the corresponding submodule contributes to the forming of the AC voltage on the AC terminal.

4. 发明公开

EP3114763A1 MULTILEVEL CONVERTER 有权
标题翻译：多级转换器
公开(公告)号：EP3114763A1
公开(公告)日：2017-01-11
申请号：EP14707805.9
申请日：2014-03-05
申请人： ABB Schweiz AG
发明人： LACHICHI, Amel , DIJKHUIZEN, Frans , HYTTINEN, Mats , NAWAZ, Muhammad , CHEN, Nan
IPC分类号： H02M7/00 , H02M7/48 , H02M7/483
CPC分类号： H02M7/003 , H02M7/48 , H02M2007/4835
摘要： A multilevel converter cell or power electronics building block (4a, 4b, 4c, 4d) for a multilevel converter comprising a half bridge module (6, 6') having a capacitor unit (8, 8') and at least two semiconductor switches (24, 24', 24'', 24'''), a gate unit (12, 12') configured to control the semiconductor switches, an electric conductor (32), at least a first and second terminal portions (33a, 33b) and a sub cell (5, 5a, 5b, 5a', 5b'). The sub cell (5, 5a, 5b, 5a', 5b') may comprise at least two half bridge modules connected in parallel and the electric conductor and the two terminal portions (33a, 33b) are configured to be connected to the sub cell in at least two different ways in order to provide a half bridge configured sub cell (5a, 5a') or a full bridge configured sub cell (5b, 5b') for the multilevel converter cell.
摘要翻译：一种用于多电平转换器的多电平转换器单元或功率电子构件块（4a，4b，4c，4d），包括具有电容器单元（8,8'）的半桥模块（6,6'）和至少两个半导体开关，用于控制半导体开关的门单元（12,12'），电导体（32），至少第一和第二端子部分（33a，33b，24,24'，24“，24” ）和子单元（5,5a，5b，5a'，5b'）。子电池（5,5a，5b，5a'，5b'）可以包括至少两个并联连接的半桥模块，并且电导体和两个端子部分（33a，33b）被配置为连接到子电池以至少两种不同的方式，以便为多电平转换器单元提供半桥配置的子电池（5a，5a'）或全桥配置的子电池（5b，5b'）。

5. 发明公开

EP3994783A1 MVDC LINK-POWERED BATTERY CHARGERS AND OPERATION THEREOF 审中-公开
公开(公告)号：EP3994783A1
公开(公告)日：2022-05-11
申请号：EP20737581.7
申请日：2020-07-02
申请人： ABB SCHWEIZ AG
发明人： BERGGREN, Bertil , MAJUMDER, Ritwik , SAERS, Robert , DIJKHUIZEN, Frans
IPC分类号： H02J3/36 , H02J7/00 , H02J7/06 , H02J7/32 , H02M5/44

6. 发明授权

EP3114763B1 MULTILEVEL CONVERTER 有权
公开(公告)号：EP3114763B1
公开(公告)日：2018-06-06
申请号：EP14707805.9
申请日：2014-03-05
申请人： ABB Schweiz AG
发明人： LACHICHI, Amel , DIJKHUIZEN, Frans , HYTTINEN, Mats , NAWAZ, Muhammad , CHEN, Nan
IPC分类号： H02M7/00 , H02M7/48 , H02M7/483
CPC分类号： H02M7/003 , H02M7/48 , H02M2007/4835
摘要： A multilevel converter cell or power electronics building block (4a, 4b, 4c, 4d) for a multilevel converter comprising a half bridge module (6, 6') having a capacitor unit (8, 8') and at least two semiconductor switches (24, 24', 24'', 24'''), a gate unit (12, 12') configured to control the semiconductor switches, an electric conductor (32), at least a first and second terminal portions (33a, 33b) and a sub cell (5, 5a, 5b, 5a', 5b'). The sub cell (5, 5a, 5b, 5a', 5b') may comprise at least two half bridge modules connected in parallel and the electric conductor and the two terminal portions (33a, 33b) are configured to be connected to the sub cell in at least two different ways in order to provide a half bridge configured sub cell (5a, 5a') or a full bridge configured sub cell (5b, 5b') for the multilevel converter cell.

7. 发明公开

EP3820040A1 MULTIPHASE CURRENT-FED MODULAR MULTILEVEL CONVERTER 无效
公开(公告)号：EP3820040A1
公开(公告)日：2021-05-12
申请号：EP19208333.5
申请日：2019-11-11
申请人： ABB Schweiz AG
发明人： ABDELHAKIM, Ahmed , DIJKHUIZEN, Frans
IPC分类号： H02M7/483 , H02M3/158
摘要： A multiphase current-fed modular multilevel converter, CMMC, is presented. The CMMC comprises a plurality of cascaded submodules, SMs, (57) connected in series between ground point and an alternating current, AC, voltage output point (V), wherein each SM comprises a connectable series capacitor (C 1 , C 2 , C n ), a blocking diode (D) connected between an input direct current, DC, source point (i dc ) and the AC voltage output point, wherein each phase of the multiphase CMMC comprises an arm of the plurality of cascaded SMs (57) and the blocking diode (D), and an input DC source (50, 51) connected between ground and the input DC source point. An output AC voltage (V a , V b , V c ) is drawn differentially between two of the arms.

8. 发明公开

EP3734827A1 BACK-TO-BACK CONVERTER ARRANGEMENT 审中-实审转让
公开(公告)号：EP3734827A1
公开(公告)日：2020-11-04
申请号：EP20172277.4
申请日：2020-04-30
申请人： ABB Schweiz AG
发明人： OKAZAKI, Yuhei , DIJKHUIZEN, Frans
IPC分类号： H02M7/219 , H02M7/483
摘要： An MMC of a back-to-back converter arrangement comprises a first and a second phase leg connected between a first DC terminal having a first DC voltage and a second DC terminal having a second DC voltage, the phase legs comprising upper and lower arms with submodules, where each submodule comprises an energy storage element and the junction between two arms provides a corresponding AC terminal. Each phase leg is controlled (42) according to a scheme for generating a waveform on the corresponding AC terminal, which control comprises controlling (42a) the upper phase arm to bypass their energy storage elements and the lower phase arm to be blocked in a first interval (TI1), controlling (42b) the upper and lower phase arms to transition from the first to the second DC voltage in a second interval (TI2), controlling (42c) the upper phase arm to be blocked and the lower phase arm to bypass their energy storage elements in a third interval (TI3), and controlling (42d) the upper and lower phase arms to transition from the second to the first DC voltage in a fourth interval (TI4).

9. 发明授权

EP3329585B1 HYBRID MODULAR MULTI-LEVEL CONVERTER 有权
公开(公告)号：EP3329585B1
公开(公告)日：2019-09-04
申请号：EP16741322.8
申请日：2016-07-21
申请人： ABB Schweiz AG
发明人： SCHWEIZER, Mario , STEIMER, Peter , DIJKHUIZEN, Frans
IPC分类号： H02M7/487

10. 发明公开

EP3329585A1 HYBRID MODULAR MULTI-LEVEL CONVERTER 有权
公开(公告)号：EP3329585A1
公开(公告)日：2018-06-06
申请号：EP16741322.8
申请日：2016-07-21
申请人： ABB Schweiz AG
发明人： SCHWEIZER, Mario , STEIMER, Peter , DIJKHUIZEN, Frans
IPC分类号： H02M7/487
CPC分类号： H02M7/487 , H02M2007/4835
摘要： A modular multi-level converter (10) for converting a DC voltage into an AC voltage comprises a first row (14) and a second row (18) of converter cells (16, 20), each converter cell (16, 20) comprising a cell capacitor (Ccell, Ccell') and semiconductor switches (34, 36, 34', 36') adapted for connecting the cell capacitor to an output of the converter cell (16, 20) and for bypassing the cell capacitor. The first row (14) of converter cells (16) interconnects a positive DC link connection point (22a) and a negative DC link connection point (22c), wherein the first row (14) of converter cells (16) comprises an upper pair and a lower pair of series-connected strings (24a, 24b, 24c, 24d) of series-connected converter cells (16), wherein the upper pair of strings (24a, 24b) connects the positive DC link connection point (22a) with a neutral DC link connection point (22b) and provides an upper intermediate connection point (26a) between the strings (24a, 24b) and the lower pair of strings (24c, 24d) connects the negative DC link connection point (22c) with the neutral DC link connection point (22b) and provides a lower intermediate connection point (26b) between the strings (24c, 24d). The second row (18) of converter cells (20) comprises a pair of strings (28a, 28b) of series-connected converter cells (20) interconnecting the upper intermediate connection point (26a) and the lower intermediate connection point (26b) and provides an AC connection point between the strings (28a, 28b). The converter cells (16) of the first row (14) have a first cell capacity (Ccell') and the converter cells (20) of the second row (18) have a second cell capacity (Ccell) higher than the first cell capacity (Ccell'). The converter cells (16) of the first row (14) have a capacitor switch (36'), which interconnects the cell capacitor (Ccell') with the outputs (38) and which has a lower current rating than a main switch (34') of the converter cells (16) of the first row (14) connected in parallel to the cell capacitor (Ccell'). The converter cells (20) of the second row (18) have a capacitor switch (36) and the current rating of the capacitor switch (36') of a converter cell (16) of the first row (14) is smaller than a current rating of the capacitor switch (36) of a converter cell (20) of the second row (18).

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