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1. 发明公开

EP2763512A1 A circuit board system comprising a cooling arrangement 审中-公开
标题翻译： Leiterplattensystem mitKühlanordnung
公开(公告)号：EP2763512A1
公开(公告)日：2014-08-06
申请号：EP14153241.6
申请日：2014-01-30
申请人： Tellabs Oy
发明人： Holma, Antti , Kohonen, Petri
IPC分类号： H05K1/02
CPC分类号： H05K1/0209 , H05K1/0204 , H05K1/0206 , H05K1/0207 , H05K1/0284 , H05K2201/09045
摘要： A circuit board system according to the invention comprises a circuit board (101), at least one electrical component (102), and a conductor part (103) in heat conducting relation with the electrical component. A surface of the circuit board comprises a portion (104) that is uneven so as to increase the surface area of the portion. The portion is coated with a coating (105) made of conductor material so that a surface of the coating is uneven. The circuit board comprises a heat conductive pathway (106) made of conductor material and extending from the conductor part to the coating. Thus, the coating operates as a cooling element for cooling the electrical component.
摘要翻译：根据本发明的电路板系统包括电路板（101），至少一个电气部件（102）和与电气部件导热的导体部分（103）。电路板的表面包括不均匀的部分（104），以增加该部分的表面积。该部分涂覆有由导体材料制成的涂层（105），使得涂层的表面不均匀。电路板包括由导体材料制成并从导体部分延伸到涂层的导热通路（106）。因此，涂层作为用于冷却电气部件的冷却元件工作。

2. 发明授权

EP2432177B1 A method and a device for controlling advertising of routing data 有权转让
标题翻译：用于控制路由数据的公布的方法和设备
公开(公告)号：EP2432177B1
公开(公告)日：2014-01-15
申请号：EP11170649.5
申请日：2011-06-21
申请人： Tellabs Oy
发明人： Hallivuori, Ville
IPC分类号： H04L12/751 , H04L12/715 , H04L12/771
CPC分类号： H04L45/02 , H04L45/025 , H04L45/04 , H04L45/54

3. 发明公开

EP2680468A2 A method and a device for controlling a clock signal generator 有权转让
标题翻译： Verfahren und Vorrichtung zur Reglung eines Taktsignalgenerators
公开(公告)号：EP2680468A2
公开(公告)日：2014-01-01
申请号：EP13171578.1
申请日：2013-06-12
申请人： Tellabs Oy
发明人： Hann, Kenneth , Lundqvist, Jonas
IPC分类号： H04J3/06
CPC分类号： G06F1/12 , H04J3/0667 , H04J3/0697 , H04L43/026
摘要： A device (104) for controlling a clock signal generator comprises a processing system configured to form a control quantity at least partly on the basis of reception moments of data frames belonging to a given flow, the reception moments being time values based on a clock signal prevailing at a receiver. The processing system controls the clock signal generator with the control quantity so as to achieve synchronization between the clock signal and another clock signal in accordance of which the data frames have been transmitted. In order to identify data frames belonging to the relevant flow, the processing system checks whether pre-determined bits of a received data frame constitute a bit pattern that occurs when the data frame belongs to the relevant flow. Therefore, the reception moments of data frames belonging to the relevant flow are obtainable without deep inspection of the received data frames.
摘要翻译：用于控制时钟信号发生器的装置（104）包括处理系统，被配置为至少部分地基于属于给定流的数据帧的接收时刻形成控制量，接收时刻是基于时钟信号的时间值盛行在接收器。处理系统以控制量控制时钟信号发生器，以便实现时钟信号与另一时钟信号之间的同步，根据该时钟信号发送数据帧。为了识别属于相关流程的数据帧，处理系统检查接收到的数据帧的预定位是否构成当数据帧属于相关流时发生的位模式。因此，在不深入检查接收的数据帧的情况下，可以获得属于相关流程的数据帧的接收时刻。

4. 发明公开

EP2458739A1 Tranceiver unit 有权
标题翻译：发件人Empfängereinheit
公开(公告)号：EP2458739A1
公开(公告)日：2012-05-30
申请号：EP11189273.3
申请日：2011-11-16
申请人： Tellabs Oy
发明人： Hann, Kenneth
IPC分类号： H03L7/07 , H04L7/00
CPC分类号： H03L7/07 , H04J3/047
摘要： A phase synchronized optical master-slave loop comprises at the slave-end a processor (105) configured to include a first timing signal into a bit stream to be transmitted to the master-end, detect a second timing signal from a bit stream received from the master-end, and calculate a phase difference between a regenerated phase signal and a reference phase signal on the basis of a transmission moment of the first timing signal, a first time-stamp indicating a reception moment of the first timing signal at the master-end, a reception moment of the second timing signal, and a second time-stamp indicating a transmission moment of the second timing signal from the master-end. The processor is configured to read the time stamps from the received bit stream that corresponds to a received light signal according to a reception line-code. Thus, conversion of data format is not necessary for the phase synchronization.
摘要翻译：相位同步的光主从环包括在从端处的处理器（105），被配置为将第一定时信号包括在要发送到主端的比特流中，从从第一定时信号接收的比特流中检测第二定时信号并且基于第一定时信号的传输力矩计算再生相位信号和参考相位信号之间的相位差，表示主机上的第一定时信号的接收力矩的第一时间戳 -end，第二定时信号的接收时刻，以及指示来自主端的第二定时信号的发送时刻的第二时间戳。处理器被配置为根据接收线路码从接收到的比特流读取对应于接收到的光信号的时间戳。因此，相位同步不需要数据格式的转换。

5. 发明公开

EP2381652A3 A method and device for network address configuration 审中-公开
标题翻译：用于网络地址配置的方法和装置
公开(公告)号：EP2381652A3
公开(公告)日：2011-11-16
申请号：EP11159307.5
申请日：2011-03-23
申请人： Tellabs Oy
发明人： Kettunen, Juhamatti
IPC分类号： H04L29/12
CPC分类号： H04L29/12933 , H04L29/12283 , H04L61/2061 , H04L61/6068
摘要： A data transfer system comprises interconnected network devices organized to constitute a hierarchical logical arrangement having at least three levels of network hierarchy. A network device (102) receives from another network device (101) that is higher at the hierarchy a first data item such as an IP-prefix defining a first set of network addresses such as IP-addresses. The network device composes second data items so that each of the second data items defines one of mutually non-overlapping sub-sets of the first set. The network device transmits the second data items to network devices (104, 105) that are lower at the hierarchy in order to allocate one of the sub-sets to each of these network devices at the lower level of the hierarchy. This procedure can be repeated on all levels of the network hierarchy. Thus, the address configuration can propagate downwards through the hierarchical logical arrangement of the network devices.

6. 发明授权

EP1476999B1 METHOD AND APPARATUS FOR IMPLEMENTING ADAPTIVE TOMLINSON-HARASHIMA PRECODING IN A DIGITAL DATA LINK 有权
标题翻译：方法和设备实现自适应TOMLINSON原岛预编码在数字数据链
公开(公告)号：EP1476999B1
公开(公告)日：2011-01-19
申请号：EP03702682.0
申请日：2003-02-19
申请人： Tellabs Oy
发明人： VÄÄNÄNEN, Janne , LAAMANEN, Heikki
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/4921 , H04L27/34
摘要： The invention relates to a method for implementing adaptive Tomlinson-Harashima precoding using a digital data communications link. According to the method, the outgoing bit stream is coded into symbols, channel distortion is corrected by precoding (TML) the symbols, the precoded symbols are sent over a data communications channel (2, CHN), in which case the symbols, which have passed through the channel (2, CHN) and signal processing means for the receiver are reconstructed to form a bit stream. According to the invention, updated precoder coefficient parameter values are formed with the aid of an error variable (e), which is dependent on the symbol decisions (S') of the receiver, the output signal of a decision-feedback equalizer, and a signal (Q) that is formed from the received signal by compensating the effect of the precoder transfer function of the received signal with an inverse precoder transfer functions.

7. 发明公开

EP1909422A3 Method and arrangement for transmitting time stamp information 审中-公开
标题翻译：用于传输时戳信息的方法和装置
公开(公告)号：EP1909422A3
公开(公告)日：2010-12-22
申请号：EP07116794.4
申请日：2007-09-20
申请人： Tellabs Oy
发明人： Laulainen, Mikko , Hann, Kenneth , Kausiala, Jorma
IPC分类号： H04J3/06 , H04L12/40
CPC分类号： H04J3/0664 , H04J3/0697 , H04J3/247 , H04L69/28
摘要： The invention relates to transmitting time information between elements of a data network. In the present invention, it has surprisingly been discovered that in a network transmitting packet, frame or cell switched data traffic, time stamp information can be transmitted from a network element (101) to another network element (102) by using that part (113a, 113c) of the bit stream (111 b) to be transmitted which is connected, in the transmitting network element (101), to the transmitted bit stream in a location that is placed, in the flowing direction of the transmitted bit stream, after a transmission buffer (103) buffering data packets, frames or cells. In an arrangement according to the invention, the random-type share of the transmission delay experienced by the time stamp information is slight, because the time stamp information does not have to queue in the transmission buffer (103) buffering data packets, frames or cells.

8. 发明公开

EP2024840A1 METHOD AND ARRANGEMENT FOR PROCESSING TRANSACTIONS IN A FLASH TYPE MEMORY DEVICE 审中-公开
标题翻译： VERFAHREN UND ANORDNUNG ZUR VERARBEITUNG VON TRANSAKTIONEN IN EINER FLASH-SPEICHERVORRICHTUNG
公开(公告)号：EP2024840A1
公开(公告)日：2009-02-18
申请号：EP07788705.7
申请日：2007-06-07
申请人： Tellabs Oy
发明人： HALLIVUORI, Matti
IPC分类号： G06F12/02 , G11C16/02
CPC分类号： G06F12/0246 , G06F9/466 , G06F9/467 , G06F11/1471 , G06F11/1474 , G06Q20/341 , G06Q20/346 , G06Q20/35765 , G07F7/084 , G07F7/1008
摘要： The invention relates to a method and arrangement for processing transactions in a flash type memory device, wherein the transaction is a data update and/or changing operation consisting of one or more suboperations, all of which must be successfully executed in order to regard the discussed transaction as having been successfully completed in its entirety. In the solution according to the invention, memory-block specific status information (131) of a memory block present in a flash type memory device is utilized not only for managing payload data (141) present in the memory block but also for the management of an entire transaction, Consequently, there is no need for a separate status bookkeeping of transactions, thus reducing the number of reading and writing operations required in transactions.
摘要翻译：本发明涉及一种用于处理闪存型存储设备中的事务的方法和装置，其中事务是由一个或多个子程序组成的数据更新和/或改变操作，所有这些操作必须被成功地执行以便考虑所讨论的交易已成功完成。在根据本发明的解决方案中，存在于闪存型存储装置中的存储块的存储块特定状态信息（131）不仅用于管理存在于存储块中的有效载荷数据（141），而且用于管理整个交易。因此，不需要对交易进行单独的状态记账，从而减少交易中所需的阅读和写作操作的数量。

9. 发明公开

EP1931069A2 Method and system for synchronizing clock signals 有权
标题翻译： VERFAHREN UND SYSTEM ZUM SYNCHRONISIEREN VON TAKTSIGNALEN
公开(公告)号：EP1931069A2
公开(公告)日：2008-06-11
申请号：EP07121473.8
申请日：2007-11-26
申请人： Tellabs Oy
发明人： Hann, Kenneth , Laamanen, Heikki , Laulainen, Mikko
IPC分类号： H04J3/06
CPC分类号： H04J3/0664
摘要： The invention relates to a method and system for adjusting a clock signal placed in a network element of a data network. The clock signal is adjusted on the basis of difference values formed by means of received synchronizing messages. Each difference value is a difference of a reception time value and a transmission value of a received synchronizing message. The reception time value of the synchronizing message depends on a cumulated number of periods of the clock signal at a moment of arrival of the synchronizing message, and the transmission value depends on a position of the synchronizing message in a chronological transmission order of the synchronizing messages. In the adjusting process, an adjusting effect of the difference values belonging to a lower part (304) of a margin of fluctuation (306) of the difference values is weighted more heavily than an adjusting effect of the difference values belonging to an upper part (305) of the margin of fluctuation of the difference values. Thus, for adjusting the clock signal, there can be used that share of information represented by the received synchronizing messages that has the least interference, irrespective of the load situation of the data network.
摘要翻译：本发明涉及一种用于调整放置在数据网络的网络元件中的时钟信号的方法和系统。基于通过接收到的同步消息形成的差值来调整时钟信号。每个差值是接收时间值和接收到的同步消息的发送值的差。同步消息的接收时间值取决于同步消息到达时刻的时钟信号的累积次数，并且发送值取决于同步消息按同步消息的时间顺序的发送顺序的位置。在调整处理中，属于差值的余量（306）的下部（304）的差分值的调整效果比属于上部的差分值的调整效果（ 305）差值波动幅度。因此，为了调整时钟信号，可以使用由接收到的具有最小干扰的同步消息表示的信息共享，而不管数据网络的负载情况如何。

10. 发明公开

EP1909422A2 Method and arrangement for transmitting time stamp information 审中-公开
标题翻译： Verfahren und Vorrichtung zurÜbertragungvon Zeitstempelinformation
公开(公告)号：EP1909422A2
公开(公告)日：2008-04-09
申请号：EP07116794.4
申请日：2007-09-20
申请人： Tellabs Oy
发明人： Laulainen, Mikko , Hann, Kenneth , Kausiala, Jorma
IPC分类号： H04J3/06 , H04L12/40
CPC分类号： H04J3/0664 , H04J3/0697 , H04J3/247 , H04L69/28
摘要： The invention relates to transmitting time information between elements of a data network. In the present invention, it has surprisingly been discovered that in a network transmitting packet, frame or cell switched data traffic, time stamp information can be transmitted from a network element (101) to another network element (102) by using that part (113a, 113c) of the bit stream (111 b) to be transmitted which is connected, in the transmitting network element (101), to the transmitted bit stream in a location that is placed, in the flowing direction of the transmitted bit stream, after a transmission buffer (103) buffering data packets, frames or cells. In an arrangement according to the invention, the random-type share of the transmission delay experienced by the time stamp information is slight, because the time stamp information does not have to queue in the transmission buffer (103) buffering data packets, frames or cells.
摘要翻译：本发明涉及在数据网络的元件之间传送时间信息。在本发明中，令人惊奇地发现，在网络发送分组，帧或小区交换数据业务中，时间戳信息可以通过使用该部分（113a）从网元（101）发送到另一网元在发送网络元件（101）中连接的要发送的比特流（111b）的数据流（113c），被发送到位于被发送的比特流的流向的位置之后的所发送的比特流缓冲数据分组，帧或小区的传输缓冲器（103）。在根据本发明的装置中，时间戳信息经历的传输延迟的随机类型共享是轻微的，因为时间戳信息不必在缓冲数据分组，帧或小区的传输缓冲器（103）中排队。

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