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1. 发明公开

EP1876712A1 CLOCK GENERATING CIRCUIT AND AUDIO SYSTEM 审中-公开
标题翻译： TAKTERZEUGUNGSSCHALTUNG UND AUDIOSYSTEM
公开(公告)号：EP1876712A1
公开(公告)日：2008-01-09
申请号：EP06715387.4
申请日：2006-03-08
申请人： Niigata Seimitsu Co., Ltd. , Ricoh Company, Ltd.
发明人： MIYAGI, Hiroshi c/o Niigata Seimitsu Co., Ltd.
IPC分类号： H03L7/08
CPC分类号： H03L7/183
摘要： A clock generating circuit having a simple constitution and an audio system are disclosed.
The clock generating circuit (300) comprises an oscillator (12) for generating a reference frequency signal by means of a crystal oscillator (10) of a resonance frequency of 32.768 kHz, a PLL circuit for generating a signal synchronizing with the reference frequency signal generated by the oscillator (12) and having a frequency which is M times the reference frequency signal, a first frequency divider (30) for generating a first clock signal (CLK1) having a frequency of 32 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N1, a second frequency divider (32) for generating a second clock signal (CLK2) having a frequency of 38 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N2, and a third frequency divider (34) for generating a third clock signal (CLK3) having a frequency of 48 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N3.
摘要翻译：公开了具有简单结构和音频系统的时钟发生电路。时钟发生电路（300）包括用于通过32.768kHz的谐振频率的晶体振荡器（10）产生参考频率信号的振荡器（12），用于产生与产生的参考频率信号同步的信号的PLL电路通过所述振荡器（12）并且具有与参考频率信号的M倍的频率的第一分频器（30），用于通过对由所述基准频率信号产生的信号进行分频来产生具有32kHz频率的第一时钟信号（CLK1） PLL电路，分频比N1的第二分频器（32），用于通过以分频比N2分频由PLL电路产生的信号来产生具有38kHz频率的第二时钟信号（CLK2）的第二分频器（32）分频器（34），用于通过以分频比N3对由PLL电路产生的信号进行分频来产生具有48kHz频率的第三时钟信号（CLK3）。

2. 发明公开

EP1796211A1 ANTENNA FOR PORTABLE TERMINAL AND PORTABLE TERMINAL 审中-公开
标题翻译：天线FÜRTRAGBARESENDGERÄTUND TRAGBARESENDGERÄT
公开(公告)号：EP1796211A1
公开(公告)日：2007-06-13
申请号：EP05748452.9
申请日：2005-06-06
申请人： Niigata Seimitsu Co., Ltd.
发明人： MIYAGI, Hiroshi; 1265-1, Shinyoshida-cho, , OKAMOTO, Akira
IPC分类号： H01Q5/01 , H01Q1/24 , H04M1/02
CPC分类号： H04B1/3805 , H01Q1/243 , H01Q1/244
摘要： When a coil I b is arranged at the forward end of an antenna element 1a which resonates with the frequency band of portable phones and an effective length of the combination the antenna element 1a and coil 1b is set equal to the length at which the frequency band of FM broadcast resonates, the coil acts as low impedance, matching to the frequency band of FM broadcast, and acts as high impedance for the frequency band of portable phones which is higher than the frequency band of FM broadcast. Consequently, the coil 1b can serve both as a matching coil for passing the frequency band of FM broadcast and a trap coil for blocking the passage of the frequency band of portable phones.
摘要翻译：当线圈Ib布置在与便携式电话的频带谐振的天线元件1a的前端，并且天线元件1a和线圈1b的有效长度被设置为等于频带的长度 FM广播谐振，线圈作为FM广播的频带匹配的低阻抗，并且对于高于FM广播的频带的便携式电话的频带起着高阻抗的作用。因此，线圈1b可以用作通过FM广播的频带的匹配线圈和用于阻止便携式电话的频带通过的陷波线圈。

3. 发明公开

EP1118946A4 DATA INTERPOLATION METHOD 审中-公开
标题翻译：数据插值
公开(公告)号：EP1118946A4
公开(公告)日：2007-05-02
申请号：EP99923950
申请日：1999-06-08
申请人： NIIGATA SEIMITSU CO LTD
发明人： KOYANAGI YUKIO , TORAICHI KAZUO
IPC分类号： H03H17/00 , G06F17/10 , G06F17/17 , G06T3/40 , G06F17/15
CPC分类号： G06T3/4007 , G06F17/17
摘要： A data interpolation method capable of reducing an operation volume without the occurrence of a truncation error. Each of four step function generators (10-1 to 10-4) generates a preset step function. Multipliers (12-1 to 12-4) each multiply step function values output from relative step function generators (10-1, etc.) by discrete data values held cyclically in data holders (11-1, etc.). An adder (14) adds together the multiplied results output from respective multipliers (12-1, etc.) in response to the respective four discrete data and the added value is integrated twice by integrators (16, 18), an interpolation value between the discrete data being then output from the second-stage integrator (18).

4. 发明公开

EP1758241A1 IMAGE REMOVING CIRCUIT 审中-公开
标题翻译： BILDENTFERNUNGSSCHALTUNG
公开(公告)号：EP1758241A1
公开(公告)日：2007-02-28
申请号：EP05743918.4
申请日：2005-05-25
申请人： Niigata Seimitsu Co., Ltd.
发明人： AOYAMA, T., KABUSHIKI KAISHA TOYOTA JIDOSHOKKI , MIYAGI, Hiroshi, NIIGATA SEIMITSU CO. LTD.
IPC分类号： H03D7/18 , H04B1/26
CPC分类号： H04B1/28 , H03D7/14
摘要： In order to provide an image rejection circuit that can reject an image signal without being affected by manufacturing variations in circuit elements such as resistors, condensers, or the like, an image rejection circuit is provided which comprises a first mixer unit 2 for mixing a signal received by a receiver device with a first local oscillation signal generated by a local oscillator 1, a secondmixer unit 3 for mixing the received signal with a second local oscillation signal obtained by shifting the local oscillation signal generated by the local oscillator 1 by 90°, a polyphase filter circuit 4 including condensers C1 and switched capacitors, and a composition/output unit 5 for composing and outputting the IF signals output from the polyphase filter circuit 4.
摘要翻译：为了提供可以抑制图像信号而不受制造电路元件如电阻器，电容器等的变化影响的图像抑制电路，提供了一种图像抑制电路，其包括用于混合信号的第一混频器单元2 由本地振荡器1产生的具有第一本地振荡信号的接收机装置接收的第二混频器单元3，用于将接收信号与通过将本地振荡器1产生的本地振荡信号移位90°而获得的第二本机振荡信号混合; 包括电容器C1和开关电容器的多相滤波器电路4和用于组合和输出从多相滤波器电路4输出的IF信号的合成/输出单元5。

5. 发明公开

EP1715591A1 FM RECEIVER 审中-公开
标题翻译： FM-EMPFÄNGER
公开(公告)号：EP1715591A1
公开(公告)日：2006-10-25
申请号：EP05709903.8
申请日：2005-02-08
申请人： KABUSHIKI KAISHA TOYOTA JIDOSHOKKI , Niigata Seimitsu Co., Ltd.
发明人： KOIKE, Tsuyoshi, c/o K.K. TOYOTA JIDOSHOKKI , MIYAGI, Hiroshi, c/o NIIGATA SEIMITSU CO., LTD.
IPC分类号： H04B1/16
CPC分类号： H04H20/88 , H04B1/1653 , H04H40/81 , Y02D70/40
摘要： An FM receiver which can be used by being switched between stereophonic and monophonic, and comprises detecting unit for detecting a received signal, two routes over which a detected signal is transmitted to an output buffer, and a switching unit for selecting either one of the two routes. The two routes consist of a route passing through a stereophonic demodulator unit and a route bypassing the stereophonic demodulator unit; and the switching unit selects either one of the two routes based on a control signal indicating the selection of either one of stereophonic and monophonic, and, when the route bypassing the stereophonic demodulator unit is selected, turns off power supply to the stereophonic demodulator unit based on the above control signal.
摘要翻译： FM接收机，其可以通过在立体声和单声道之间切换而使用，并且包括用于检测接收信号的检测单元，将检测信号发送到输出缓冲器的两个路由，以及用于选择两个中的任一个的切换单元路线。两条路线由通过立体声解调器单元的路线和绕过立体声解调器单元的路线组成，并且所述切换单元基于指示选择立体声和单声道中的任一个的控制信号来选择所述两条路线中的任一条路线，并且当选择旁路所述立体声解调器单元的路线时，关闭对所述立体声解调器单元的电力供应上述控制信号。

6. 发明公开

EP1710915A1 IF COUNTING METHOD 审中-公开
标题翻译： ZF-ZÄHLVERFAHREN
公开(公告)号：EP1710915A1
公开(公告)日：2006-10-11
申请号：EP05709238.9
申请日：2005-01-07
申请人： KABUSHIKI KAISHA TOYOTA JIDOSHOKKI , Niigata Seimitsu Co., Ltd.
发明人： GOTO, S., Kabushiki Kaisha Toyota Jidoshokki , MIYAGI, Hiroshi, Niigata Seimitsu Co., Ltd.
IPC分类号： H03K21/40
CPC分类号： H03K21/40
摘要： In order to provide an IF counting method for realizing an IF counter with a smaller circuit configuration, an IF counter comprises a countdown IF counting unit 1 for counting frequency-divided IF signals, an IF count time period determination unit 2 for determining a count time period, an IF count upper limit presetting unit 3 for providing the countdown IF counting unit 1 with an initial value, a lower-order m-bit comparison unit 5 for comparing the lower-order m bits of the value counted by the countdown IF counting unit 1 with information preset in the IF count upper/lower limit difference presetting unit 3 and a determination unit 6 for determining whether the count value is within a prescribed range, according to the higher-order (n+1-m) bits of the value counted by the countdown IF counting unit 1 and the comparison result of the lower-order m-bit comparison unit.
摘要翻译：为了提供用于实现具有较小电路配置的IF计数器的IF计数方法，IF计数器包括用于对分频的IF信号进行计数的倒计时IF计数单元1，用于确定计数时间的IF计数时间段确定单元2 周期，用于提供具有初始值的倒计时IF计数单元1的IF计数上限预设单元3，用于比较通过倒数IF计数计数的值的低位m位的低阶m位比较单元5 具有在IF计数上限/下限差分预设单元3中预设的信息的单元1以及用于根据所述高阶（n + 1-m）比特来确定计数值是否在规定范围内的确定单元6 由倒计时IF计数单元1计数的值和下位m位比较单元的比较结果。

7. 发明公开

EP1635454A1 LOW-NOISE AMPLIFIER 审中-公开
标题翻译： RAUSCHARMERVERSTÄRKER
公开(公告)号：EP1635454A1
公开(公告)日：2006-03-15
申请号：EP04745811.2
申请日：2004-06-11
申请人： KABUSHIKI KAISHA TOYOTA JIDOSHOKKI , Niigata Seimitsu Co., Ltd. , OHMI, Tadahiro
发明人： OHMI, Tadahiro , NISHIMUTA, Takefumi , MIYAGI, Hiroshi , SUGAWA, Shigetoshi , TERAMOTO, Akinobu
IPC分类号： H03F1/26 , H03F3/19 , H01L27/08 , H01L29/78
CPC分类号： H01L21/82385 , H01L21/823807 , H01L27/092 , H01L29/785 , H03F1/26 , H03F2200/372 , H03G1/0029 , H03G1/007
摘要： A low noise amplifier is assumed to comprise an MIS transistor and to amplify an input signal keeping noise at a low level, and the MIS transistor comprises a semiconductor substrate for comprising a first crystal plane as a principal plane, a semiconductor structure, formed as a part of the semiconductor substrate, for comprising a pair of sidewall planes defined by the second crystal plane different from the first crystal plane and a top plane defined by the third crystal plane different from the second crystal plane, a gate insulator of uniform thickness covering the principal plane, the sidewall planes and the top plane, a gate electrode for continuously covering the principal plane, the sidewall planes and the top plane on top of the gate insulator, and a single conductivity type diffusion area formed in the region to either side of the gate electrode in the semiconductor substrate and the semiconductor structure and continuously extending along the principal plane, the sidewall planes and the top plane.
Such a configuration allows significant reduction of the 1/f noise and the signal distortion applied to an output signal by the low noise amplifier and therefore a circuit for compensating for the reduction of the amplitude is no longer of necessity, allowing reduction in size.
摘要翻译：假设低噪声放大器包括MIS晶体管，并且将保持噪声处于低电平的输入信号放大，并且MIS晶体管包括用于包括第一晶面作为主平面的半导体衬底，形成为半导体衬底的一部分，用于包括由不同于第一晶体面的第二晶体面限定的一对侧壁平面和由不同于第二晶体面的第三晶体面限定的顶面，覆盖主平面，侧壁平面和顶面，用于连续覆盖主平面，侧壁平面和栅极绝缘体顶部的顶面的栅极，以及形成在该区域中的单一导电型扩散区域半导体衬底中的栅电极和半导体结构，并且沿着主平面连续延伸，侧壁p 车道和顶层飞机。这样的结构允许通过低噪声放大器显着降低1 / f噪声和施加到输出信号的信号失真，因此不再需要用于补偿幅度减小的电路，从而允许尺寸减小。

8. 发明公开

EP1566883A2 LC oscillator 审中-公开
标题翻译： LC-Oszillator
公开(公告)号：EP1566883A2
公开(公告)日：2005-08-24
申请号：EP05103450.2
申请日：2000-07-24
申请人： Niigata Seimitsu Co., Ltd.
发明人： Okamoto, Akira , Ikeda, Takeshi
IPC分类号： H03B5/18 , H03B5/12 , H01F17/00 , H01L23/64 , H03H1/00
CPC分类号： H03B5/1841 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/38 , H01F2017/0046 , H01L23/522 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H03B5/1203 , H03B5/1231 , H03B5/1243 , H03B2201/0208 , H01L2924/00
摘要： An LC oscillator capable of oscillating even if it is fabricated on a substrate comprises a transistor, capacitor, and an inductor element 30. The inductor element 30 has two spiral conductors 120, 122 having substantially the same shape and formed on a semiconductor substrate 110. The inner end of the conductor 120 is electrically connected to the outer end of the conductor 122. Lead wires 130, 132 are connected to the outer and inner ends of the conductor 120 respectively. The lead wire 132 is passed through the lower conductor 122 and the semiconductor substrate 110 and led outside. The upper conductor 120 serves as an inductor conductor and is connected to another component of the LC oscillator formed on the semiconductor substrate 110 through the lead wires 130, 132.
摘要翻译：即使制造在衬底上也能够振荡的LC振荡器包括晶体管，电容器和电感器元件30.电感器元件30具有两个基本相同形状的螺旋形导体120,122，形成在半导体衬底110上。导体120的内端电连接到导体122的外端。导线130,132分别连接到导体120的外端和内端。引线132穿过下导体122和半导体衬底110并被引导到外部。上导体120用作电感器导体，并且通过引线130,132连接到形成在半导体衬底110上的LC振荡器的另一部件。

9. 发明公开

EP1530310A1 SEPARATION ADJUSTING CIRCUIT 有权
标题翻译：电路是否间隔调节
公开(公告)号：EP1530310A1
公开(公告)日：2005-05-11
申请号：EP03736296.9
申请日：2003-06-27
申请人： Kabushiki Kaisha Toyota Jidoshokki , Niigata Seimitsu Co., Ltd.
发明人： KOIKE, Tsuyoshi , MIYAGI, Hiroshi c/o NIIGATA SEIMITSU CO., LTD.
IPC分类号： H04H5/00
CPC分类号： H04B1/1676 , H04B1/1646 , H04B1/1661 , H04H40/63
摘要： A current amount of a current that flows in the transistor (23) of a current mirror circuit that retrieves an L-R component signal from a stereo composite signal is adjusted based on a control signal that is generated by the control circuit (25).

10. 发明公开

EP1473841A4 SEMICONDUCTOR INTEGRATED CIRCUIT FOR RADIO APPARATUS AND RADIO COMMUNICATION APPARATUS 审中-公开
标题翻译：半导体集成电路用于无线设备和无线电通信设备
公开(公告)号：EP1473841A4
公开(公告)日：2005-03-23
申请号：EP03737468
申请日：2003-02-03
申请人： TOYOTA JIDOSHOKKI KK , NIIGATA SEIMITSU CO LTD
发明人： MIYAGI HIROSHI
IPC分类号： H03J1/00 , H03J3/08 , H03J3/28 , H03J5/02 , H03M1/66 , H04B1/16 , H04B1/18 , H04B1/26
CPC分类号： H04B1/16 , H03J1/0033 , H04B1/18
摘要： Adjustment data of a first and a second tracking adjustment circuit (11, 12) is set in latch circuits (21, 22). A plurality of adjustment data latched in the latch circuits (21, 22) are output at different timings to one D/A converter (41). The data is converted into a DC control voltage in the D/A converter (41) and the control voltage is held in voltage holding circuits of the first tracking adjustment circuit (11) and the second tracking adjustment circuit (12) for performing adjustment of tuning frequency. When an optimal tuning frequency is obtained, the tuning data at that moment is written into a non-volatile memory in the IC, so that control voltage is supplied to the respective tuning circuits according to the tuning data stored in the non-volatile memory.

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