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1. 发明公开

EP4446870A1 TENSOR CALCULATION UNIT AND USE METHOD, AND DATA PROCESSING APPARATUS AND OPERATION METHOD 审中-实审
公开(公告)号：EP4446870A1
公开(公告)日：2024-10-16
申请号：EP23892911.1
申请日：2023-03-06
申请人： Hygon Information Technology Co., Ltd.
发明人： ZUO, Hang
IPC分类号： G06F7/485
CPC分类号： G06T1/20 , G06F9/38 , G06F7/487 , G06F7/485
摘要： A tensor calculation unit and a use method, and a data processing apparatus and an operation method. The tensor calculation unit comprises a first multiply-add operator and a second multiply-add operator, which are cascaded, wherein the first multiply-add operator comprises a first input port, a second input port, a third input port and a first output port, the first input port, the second input port and the third input port are used for respectively receiving parameters A0, B0 and C, and the first multiply-add operator is configured to perform the calculation of D0 = A0 × B0 +C, and output a calculation result D0 at the first output port; and the second multiply-add operator comprises a fourth input port, a fifth input port, a sixth input port and a second output port, the fourth input port and the fifth input port are used for respectively receiving parameters A1 and B1, the sixth input port is coupled to the first output port so as to receive the calculation result D0, and the second multiply-add operator is configured to perform the calculation of D1 = A1 × B1 + D0, and output a calculation result D1 at the second output port. The tensor calculation unit can be infinitely extended and stacked.

2. 发明公开

EP4345619A1 PROCESSOR, PHYSICAL REGISTER MANAGEMENT METHOD, AND ELECTRONIC APPARATUS 审中-实审
公开(公告)号：EP4345619A1
公开(公告)日：2024-04-03
申请号：EP22862733.7
申请日：2022-05-17
申请人： Hygon Information Technology Co., Ltd.
发明人： YU, Yaxuan
IPC分类号： G06F9/50
摘要： A processor, a physical register management method, and an electronic apparatus. The processor comprises: a plurality of physical registers, which are configured to be multiplexed by a plurality of threads are run on the processor, and a thread information storage apparatus, which is configured to record a correlation between the plurality of physical registers and the plurality of threads. A correlation between a physical register and a thread is recorded by using a thread information storage apparatus, such that when a physical register number is broadcasted in error due to a fault occurring in hardware or for another reason, error correction can be realized in a timely manner, thereby preventing a subsequent series of errors and ensuring the normal operation of a processor.

3. 发明公开

EP4425327A1 DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE 审中-实审
公开(公告)号：EP4425327A1
公开(公告)日：2024-09-04
申请号：EP23884011.0
申请日：2023-02-27
申请人： Hygon Information Technology Co., Ltd.
发明人： CUI, Zehan
IPC分类号： G06F9/38
CPC分类号： Y02D10/00
摘要： Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method comprises: generating an instruction fetch request carrying at least one switching mark, the switching mark at least indicating an instruction position for decoder group switching; in response to micro-ops obtained from decoding by decoder groups, acquiring an instruction stream fetched by means of the instruction fetch request, and according to the switching mark carried in the instruction fetch request, determining the instruction position for decoder group switching; according to the instruction position, distributing the instruction stream to multiple decoder groups for parallel decoding, and carrying a switching mark in a target micro-op obtained by decoding a target instruction, the target instruction being an instruction corresponding to the instruction position; and in response to searching a micro-op cache for micro-ops, if the instruction fetch request is hit in the micro-op cache, acquiring a corresponding micro-op from the micro-op cache. The embodiments of the present disclosure can improve the decoding performance of a processor.

4. 发明公开

EP4421660A1 DATA PROCESSING METHOD AND APPARATUS, AND ELECTRONIC DEVICE AND STORAGE MEDIUM 审中-实审
公开(公告)号：EP4421660A1
公开(公告)日：2024-08-28
申请号：EP23889857.1
申请日：2023-09-14
申请人： Hygon Information Technology Co., Ltd.
发明人： HAN, Jie
IPC分类号： G06F17/16
CPC分类号： G06F17/16 , G06F9/448
摘要： A data processing method and apparatus, an electronic device, and a storage medium are disclosed, and the data processing method includes: acquiring input matrix data, in which the input matrix data is a symmetric tridiagonal matrix; performing one or more matrix splits on the input matrix data to obtain a plurality of pieces of leaf node data; performing parallel computation on the plurality of pieces of leaf node data, to obtain a feature parameter of each piece of leaf node data among the plurality of pieces of leaf node data; performing at least one merge on the plurality of pieces of leaf node data, based on the feature parameter of the each piece of leaf node data, to obtain merged data; and performing feature solving on the input matrix data based on the merged data, to obtain a feature parameter of the input matrix data. The data processing method improves a resource invocation and utilization mode of a processor apparatus, which can fully invoke the resources of the processor apparatus for computing the plurality of pieces of leaf node data in a parallel manner, thereby alleviating the resource idle problem in the processor apparatus, and improving the computational efficiency of feature solving of the symmetric tridiagonal matrix in the processor apparatus.

5. 发明公开

EP4421637A1 DATA PROCESSING METHOD AND PROCESSING APPARATUS, AND STORAGE SYSTEM 审中-实审
公开(公告)号：EP4421637A1
公开(公告)日：2024-08-28
申请号：EP23869298.2
申请日：2023-03-06
申请人： Hygon Information Technology Co., Ltd.
发明人： ZHOU, Peng , XIE, Sam , WANG, Yuxuan
IPC分类号： G06F11/10 , G11C29/42
摘要： The disclosure provides a data processing method and apparatus, and a storage system. The data processing method comprises reading two sets of burst data from a first storage channel and reading two sets of burst data from a second storage channel to obtain four sets of burst data, the four sets of burst data correspond to encoded data stored in the first storage channel and the second storage channel, the encoded data is obtained by encoding k data symbols that are written into the first storage channel and the second storage channel, and the encoded data comprises the k data symbols and m check symbols, a total bit width of the m check symbols is eight times a bit width of one error correcting symbol; organizing the four sets of burst data into a group of error correcting codewords, the group of error correcting codewords comprises k read-back data symbols and m read-back check symbols; and performing a decoding operation based on the group of error correcting codewords to obtain an error-corrected symbol. The data processing method can implement the simultaneous error correction of two symbols.

6. 发明公开

EP4411816A1 ELECTRONIC PACKAGE, ELECTRONIC PACKAGING METHOD, METHOD FOR POWER SUPPLY IN ELECTRONIC PACKAGE, AND CHIP 审中-实审
公开(公告)号：EP4411816A1
公开(公告)日：2024-08-07
申请号：EP23869280.0
申请日：2023-09-26
申请人： Hygon Information Technology Co., Ltd.
发明人： DU, Shuan , MENG, Fanxiao , YANG, Xiaojun , YANG, Guanglin , YU, Qin
IPC分类号： H01L25/07 , H01L23/48 , H01L23/31
摘要： Embodiments of the disclosure provide an electronic packaging, an electronic packaging method, a supply power method in the electronic packaging, a chip, and an electronic device. The electronic packaging includes a packaging substrate, a transferring substrate and at least two dies. The packaging substrate includes a cavity, the cavity exposes a first surface of the packaging substrate, the transferring substrate is arranged in the cavity and is connected with the first surface; a first portion of the at least two dies is connected with the packaging substrate, and a second portion of the at least two dies is connected with the transferring substrate; the packaging substrate includes a first power supply layer; the second portion of the at least two dies is electrically connected with the first power supply layer through the transferring substrate, so that the first power supply layer supplies power to an electrical component in the second portion of the at least two dies. The technical solution of the disclosure is applied in a case of chip electric packaging.

7. 发明公开

EP4394628A1 CODE PROTECTION SYSTEM AND METHOD, VIRTUAL SYSTEM ARCHITECTURE, CHIP AND ELECTRONIC DEVICE 审中-实审
公开(公告)号：EP4394628A1
公开(公告)日：2024-07-03
申请号：EP23820730.2
申请日：2023-03-03
申请人： Hygon Information Technology Co., Ltd.
发明人： YING, Zhiwei
IPC分类号： G06F21/12
摘要： The present disclosure provides a code protection system, a method, a virtual system architecture, a chip, and an electronic device, and the system includes: a heterogeneous acceleration resource configured for the code protection system, in which the heterogeneous acceleration resource is configured to execute a code execution task of a piece of software, and the code execution task includes running code of the software and/or accessing data of the software; a heterogeneous acceleration module, which is configured to allocate the code execution task to the heterogeneous acceleration resource configured for the code protection system; and a heterogeneous acceleration driving module, which is configured to drive the heterogeneous acceleration resource configured, to execute the code execution task allocated. The embodiments of the present disclosure are capable of enhancing the computing power of code protection solutions.

8. 发明公开

EP4336352A1 INSTRUCTION EXECUTION METHOD, PROCESSOR AND ELECTRONIC APPARATUS 审中-实审
公开(公告)号：EP4336352A1
公开(公告)日：2024-03-13
申请号：EP22902725.5
申请日：2022-05-17
申请人： Hygon Information Technology Co., Ltd.
发明人： HUANG, He
IPC分类号： G06F9/30
摘要： An instruction execution method, a processor and an electronic apparatus. The instruction execution method comprises: according to a selection signal, switching the pipeline structure of a processor between a first instruction execution mode and a second instruction execution mode, wherein the first instruction execution mode supports N threads and is suitable for a first general-purpose register set of an instruction set; the second instruction execution mode supports M threads and is suitable for a second general-purpose register set of the instruction set; the first general-purpose register set is less than the second general-purpose register set; M and N are positive integers; and N is greater than M.

9. 发明公开

EP4432210A1 DATA PROCESSING METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM 审中-实审
公开(公告)号：EP4432210A1
公开(公告)日：2024-09-18
申请号：EP23892910.3
申请日：2023-03-06
申请人： Hygon Information Technology Co., Ltd.
发明人： ZUO, Hang
IPC分类号： G06T1/20 , G06T1/60 , G06F9/54
CPC分类号： G06T1/60 , G06T1/20 , G06F9/54
摘要： A data processing method, a data processing apparatus, an electronic device, and a computer-readable storage medium. The data processing method is applied to a data processing apparatus. The data processing apparatus comprises a plurality of computing modules, wherein each of the plurality of computing modules comprises a plurality of thread execution units and a shared memory shared by the plurality of thread execution units, and the plurality of computing modules comprise a first computing module and a second computing module. The data processing method comprises: by means of a data transmission channel established between the shared memory of the first computing module and the shared memory of the second computing module, directly transmitting data to be exchanged between a first workgroup run by the first computing module and a second workgroup run by the second computing module. This method can shorten a data reading path, accelerate a data reading speed, and reduce the bandwidth requirements on a global memory reading path.

10. 发明公开

EP4425368A1 CHIP INTERNAL VOLTAGE PREDICTION MODEL GENERATION METHOD, CHIP INTERNAL VOLTAGE PREDICTION METHOD, AND RELATED APPARATUSES 审中-实审
公开(公告)号：EP4425368A1
公开(公告)日：2024-09-04
申请号：EP23892753.7
申请日：2023-09-14
申请人： Hygon Information Technology Co., Ltd.
发明人： DAI, Kaiyong , YANG, Yi , FU, Xingfei , PAN, Yu
IPC分类号： G06F30/367
CPC分类号： Y02D10/00
摘要： Embodiments of the present disclosure provide a generation method for a chip internal voltage prediction model, a prediction method, and related apparatuses. The generation method for the chip internal voltage prediction model includes: obtaining a load data set and a relevant index data set of a chip respectively; calibrating the relevant index data set according to a calibration cycle number and obtaining a calibrated relevant index data set; and training the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set, and obtaining the chip internal voltage prediction model with completed training. The method provided by the embodiments of the present disclosure can predict the situation of the chip internal voltage in advance, so that timely intervention can be made in the operating status of the chip.

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