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1. 发明公开

EP1324851A1 POLYMER COLLAR FOR SOLDER BUMPS 审中-公开
标题翻译：聚合物外滩颠簸
公开(公告)号：EP1324851A1
公开(公告)日：2003-07-09
申请号：EP01971260.3
申请日：2001-09-21
申请人： Flip Chip Technologies L.L.C.
发明人： ELENIUS, Peter , KIM, Deok-Hoon
IPC分类号： B23K1/20 , B23K31/02
CPC分类号： B23K3/0623 , H01L21/4853 , H01L23/49816 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/10126 , H01L2224/11334 , H01L2224/13099 , H01L2224/13565 , H01L2224/16225 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01043 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/351 , H05K3/3436 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2224/05599
摘要： A method of forming a polymer support ring, or collar, around the base of solder balls (30/32) used to form solder joints includes forming patterned regions (26/28) of uncured polymer material over each of the conductive solder bump pads (22/24) on an IC package or other substrate (20) to which the solder balls are to be attached. Preferably, the uncured polymer material is a no-flow underfill material that fluxes the solder bump pads. Pre-formed solder balls are then placed into the uncured polymer material onto their respective solder bump pads. A subsequent heating cycle raises the assembly to the reflow temperature of the solder balls, thereby attaching the solder balls to the underlying solder bump pads, and at least partially curing the polymer material to form a support collar at the base region of each attached solder ball.

2. 发明授权

EP1664936B1 PHOTOMASK AND METHOD OF FORMING A PARTIAL-DEPTH FEATURE IN A POLYMER FILM 有权
标题翻译：光掩膜和方法以减少的深度的结构元素在聚合物薄膜培训
公开(公告)号：EP1664936B1
公开(公告)日：2013-12-04
申请号：EP04809811.5
申请日：2004-09-27
申请人： Flip Chip Technologies, L.L.C.
发明人： JOHNSON, Michael, E. , ELENIUS, Peter
IPC分类号： G03F1/38 , G03F1/32 , G03F1/00
CPC分类号： G03F1/50

3. 发明公开

EP1036414A1 CHIP SCALE PACKAGE USING LARGE DUCTILE SOLDER BALLS 有权
标题翻译： HERSTELUNGSMETHODE典型大DUKTIELEN焊球甲CSP封装
公开(公告)号：EP1036414A1
公开(公告)日：2000-09-20
申请号：EP98953717.0
申请日：1998-10-19
申请人： Flip Chip Technologies L.L.C.
发明人： ELENIUS, Peter , HOLLACK, Harry
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , G06F1/1601 , G06F2200/1612 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05647 , H01L2224/10 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01051 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A chip scale package design (8) for a flip chip integrated circuit (10) includes a redistribution metal layer upon the upper surface of a semiconductor wafer (14) for simultaneaously forming solder bump pads (26) as well as the metal redistribution traces (30) that electrically couple such solder bump pads with the condutive bond pads (18) of the underlying integrated circuit (10). A patterned passivation layer (32) is applied over the redistribution metal layer (30). Relatively large, ductile solder balls (28) are placed on the solder bump pads (26) for mounting the chip scale package (8) to a circuit board or other substrate without the need for an underfill material. The back side (16) of the semiconductor wafer can be protected by a coating (34) for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

4. 发明公开

EP1665363A2 WAFER-LEVEL MOAT STRUCTURES 审中-公开
标题翻译：晶片级MOAT结构
公开(公告)号：EP1665363A2
公开(公告)日：2006-06-07
申请号：EP04785094.6
申请日：2004-09-27
申请人： Flip Chip Technologies L.L.C.
发明人： JOHNSON, Michael, E. , ELENIUS, Peter , KIM, Deok Hoon
IPC分类号： H01L21/66
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05567 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
摘要翻译：晶圆级CSP（200）包括来自晶圆的至少一个管芯（202）。晶圆级CSP具有多个焊球垫（206），每个焊球垫处的焊球（308）以及每个焊球周围的聚合物套环（310）。在制造晶片级CSP期间，在设置在晶片上的聚合物层（412）的表面中形成沟槽（204）。当晶片被加热到锡球的回流温度时发生的来自聚合物套环的暂时液化残留物（502）从聚合物套环流出。护城河是物质流动的屏障，限制了液化时残留物的扩散距离。来自聚合物套环的残留物保持在由护城河界定的区域（314）内。全深度壕沟（312）完全延伸穿过聚合物层。或者，部分深度沟槽（712和912）部分延伸穿过聚合物层。提交摘要的理解是，根据37 C.F.R，它不会用于解释或限制权利要求的范围或含义。 §1.72（b）中。

5. 发明公开

EP1664936A2 FORMING PARTIAL-DEPTH FEATURES IN POLYMER FILM 有权
标题翻译：光掩膜和方法以减少的深度的结构元素在聚合物薄膜培训
公开(公告)号：EP1664936A2
公开(公告)日：2006-06-07
申请号：EP04809811.5
申请日：2004-09-27
申请人： Flip Chip Technologies L.L.C.
发明人： JOHNSON, Michael, E. , ELENIUS, Peter
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F1/50
摘要： A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101-2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature. The photomask may also have chrome of width greater than the critical dimension and spaced from other chrome by a distance greater than the critical dimension, which produces a full-depth feature through the entire thickness of the polymer film. The partial-depth feature and the full-depth feature are produced substantially simultaneously during a single series of photo-imaging steps. By preselecting a size, shape and distance between the chrome, the photomask is capable of inscribing discernable markings on the polymer layer, of changing the thickness of the polymer layer, and of changing an optical property of the surface of the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. § 1.72(b).

6. 发明公开

EP1305829A1 SOLDER BAR FOR HIGH POWER FLIP CHIPS 有权
标题翻译： Lötleiste对于高倒装晶片
公开(公告)号：EP1305829A1
公开(公告)日：2003-05-02
申请号：EP01935623.7
申请日：2001-05-17
申请人： Flip Chip Technologies L.L.C.
发明人： ELENIUS, Peter , YANG, Hong
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5386 , H01L21/4853 , H01L23/49816 , H01L23/49838 , H01L2224/0401 , H01L2224/05552 , H01L2224/13012 , H01L2224/14051 , H01L2924/01322 , H01L2924/01327 , H01L2924/10253 , H05K3/341 , H05K3/3436 , H01L2924/00 , H01L2924/00012
摘要： A solder bar compatible with conventional flip chip technology fabrication methods for high power/high current applications includes first and second generally circular solder pads of diameter D formed upon a substrate and connected by a solder bar pad of width BW. The centers of the generally circular solder pads are spaced apart by distance BL (bar length). A mass of solder having volume VB is formed over the first and second generally circular solder pads and over the solder bar pad to form a dog-bone shaped solder bar. The solder bar reaches height H 1 above the centers of the first and second generally circular solder pads, and reaching height H 2 above the midpoint of the solder bar pad. The values for diameter D, bar length BL, bar width BW, and solder volume VB are selected in such manner that H 1 and H 2 are approximately equal. Conventional circular (as viewed from above) solder bumps can be formed upon the same substrate; in this case, heights H 1 and H 2 are made approximately equal to the height of the conventional solder bumps.

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