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    • 2. 发明公开
    • POLISHING APPARATUS
    • POLIERVORRICHTUNG
    • EP1558426A1
    • 2005-08-03
    • EP03770126.5
    • 2003-11-04
    • EBARA CORPORATION
    • HAYAMA, Takuji,Ebara CorporationINOUE, Masafumi,c/o Ebara CorporationSAKURAI, Kunihiko,c/o Ebara Corporation
    • B24B37/04H01L21/304
    • B24B47/22B24B37/30B24B49/16H01L21/30625
    • A polishing apparatus has a polishing table (12) with a polishing surface (10) attached thereon, and a top ring (20) for pressing a workpiece (W) against the polishing surface (10). The top ring (20) has a housing (40) and a retainerring (44) vertically movable in the housing (40) for holding an outer circumferential edge of the workpiece (W). The polishing apparatus includes a vertically moving mechanism operable to vertically move the top ring (20), a bracket (28) vertically movable together with the top ring (20), a stopper (32) adjustable in vertical position to prevent downward movement of the bracket (28), and a sensor (36) for detecting a distance between the stopper (32) and the bracket (28). The polishing apparatus also includes a control unit (34) operable to adjust the stopper (32) in vertical position based on the distance signal from the sensor (36).
    • 抛光装置具有安装有研磨面(10)的研磨台(12)和用于将工件(W)压靠在研磨面(10)上的顶环(20)。 顶环(20)具有壳体(40)和可在壳体(40)中垂直移动的保持环(44),用于保持工件(W)的外圆周边缘。 所述抛光装置包括可垂直移动所述顶环(20)的垂直移动机构,与所述顶环(20)一起可垂直移动的托架(28);可在垂直位置调整的止动件(32),以防止所述顶环 支架(28)和用于检测止动件(32)和支架(28)之间的距离的传感器(36)。 抛光装置还包括控制单元(34),当保持环(44)与抛光表面(10)接触时,可操作以在垂直位置调节止动器(32),而壳体(40)的下表面 所述顶环(20)的距离与所述研磨面(10)的预定高度相对应,使得所述止动件(32)与所述支架(28)之间的距离等于所述下表面 在抛光时来自抛光表面(10)的壳体(40)和预定高度。
    • 3. 发明公开
    • UNINTERRUPTED POWER SUPPLY WITH POWER-FACTOR CORRECTING BYPASS MODE
    • 带功率因数校正旁路模式的不间断电源
    • EP1556943A1
    • 2005-07-27
    • EP03777887.5
    • 2003-10-27
    • Eaton Power Quality Corporation
    • TAIMELA, Pasi, S.
    • H02M5/00H02J9/06
    • H02M1/4258H02J3/32H02J9/062H03F2200/351Y02B70/126
    • A power supply apparatus (100), such as an uninterruptible power supply, includes an AC input (101) configured to be coupled to an AC power source (1') and an AC output (102). The apparatus also includes an AC/DC converter circuit (110), e.g., a boost rectifier circuit, with an input coupled to the AC input (101). The apparatus further includes a DC/AC converter circuit (120), e.g., an inverter circuit, configured to be coupled between an output of the AC/DC converter circuit (110) and the AC output (102). A bypass circuit (S1) is operative to establish a coupling between the AC input (101) to the AC output (102) in a first (e.g., bypassed) state and to interrupt the coupling in a second (e.g., on line ) state. The AC/DC converter circuit (110) is operative to control current at the AC input (101) when the bypass circuit is in the first state. For example, the AC/DC converter circuit (110) may be operative to control current at the AC input (101) to correct a power factor at the AC input port when bypassed, such that the AC/DC converter circuit (110) may act as a line conditioner in the bypassed state.
    • 诸如不间断电源之类的电源装置(100)包括被配置为耦合到AC电源(1')和AC输出(102)的AC输入(101)。 该设备还包括具有耦合到AC输入(101)的输入的AC / DC转换器电路(110),例如升压整流器电路。 该设备还包括被配置为耦合在AC / DC转换器电路(110)的输出和AC输出(102)之间的DC / AC转换器电路(120),例如逆变器电路。 旁路电路(S1)用于在第一(例如,旁路)状态下建立AC输入(101)与AC输出(102)之间的耦合并且以第二(例如,在线)状态中断耦合 。 当旁路电路处于第一状态时,AC / DC转换器电路(110)可操作以控制AC输入(101)处的电流。 例如,AC / DC转换器电路(110)可以操作以控制AC输入(101)处的电流以在旁路时校正AC输入端口处的功率因数,使得AC / DC转换器电路(110)可以 在旁路状态下充当线路调节器。
    • 6. 发明公开
    • Tone generator apparatus sharing parameters among channels
    • 对于在信道之间共享的参数乐音发生器
    • EP1267560A3
    • 2005-07-20
    • EP02012466.5
    • 2002-06-11
    • YAMAHA CORPORATION
    • Mukojima, Masahiro
    • H04M19/00
    • H04M19/04
    • A music apparatus generates a plurality of music tones arranged in a set of performance parts of a music piece from a plurality of channels based on sequence data. A tone generator has a plurality of tone generating elements in correspondence to the plurality of the channels for generating therethrough the music tones in parallel manner. An assigning section assigns the plurality of the channels to the set of the performance parts such that each performance part may involve one or more of the channels. A sequencer processes the sequence data to sequentially provide parameters for use in the tone generating elements, the sequencer being operative when the assigning section assigns two or more channels to one performance part for providing first parameters set individually to each of said two or more channels and a second parameter set commonly to said two or more channels assigned to said one performance part. A register is divided into a first area for storing the first parameters provided from the sequencer and a second area for storing the second parameter provided from the sequencer. Each tone generating element uses both of the stored first parameter and second parameter set to the corresponding channel and characterized by both of the first and second parameters.
    • 9. 发明公开
    • Distribution of error correction and compression processing
    • Verteilung von Fehlerkorrektur und Kompressionverarbeitung
    • EP1014644A3
    • 2005-07-13
    • EP99125410.3
    • 1993-05-14
    • ROCKWELL INTERNATIONAL CORPORATION
    • Chan, Virginia, c/o Rockwell Int.Corp.MacCrisken, John E.Fisher, David W.
    • H04L29/06
    • H04M11/06H04L29/06H04L69/04H04L69/324
    • A method and apparatus for distributing the data error correction and compression processing load between a modem (DCE) and a host data terminal equipment (DTE) enables modem implementation with minimal cost, power dissipation, and size. The DTE has a CPU and an associated memory. The memory contains a data transmission program for execution by the CPU to produce output data for transmitting, and at least a data compression algorithm and a data error checking algorithm for execution by the CPU under control of the data transmission program to asynchronously deliver data according to the data transmission program to a modem for synchronous transmission. The modem included in the DCE asynchronously received the data from the DTE and synchronously transmits it as output data. Due to the distribution of the data processing algorithms into the memory of the DTE, the DCE can be operated simultaneously in communication and control modes. Moreover, the modem can be controlled during data transmission or reception in response to a 〈DLE〉 code in combination with a predetermined control code.
    • 用于在调制解调器(DCE)和主机数据终端设备(DTE)之间分配数据纠错和压缩处理负载的方法和装置以最小的成本,功耗和尺寸实现调制解调器的实现。 DTE具有CPU和相关的内存。 存储器包含用于由CPU执行以产生用于发送的输出数据的数据传输程序,以及用于在数据传输程序的控制下由CPU执行的数据压缩算法和数据错误检查算法,以根据数据传输程序异步传送数据 数据传输程序到调制解调器进行同步传输。 包含在DCE中的调制解调器异步地从DTE接收数据,同步地将其作为输出数据发送。 由于数据处理算法分配到DTE的存储器中,DCE可以在通信和控制模式下同时工作。 此外,可以在数据发送或接收期间响应于&Lang&DLE&Rang&code与预定控制码的组合来调制调制解调器。
    • 10. 发明公开
    • Multi-stage NCO
    • Mehrstufiger numerisch gesteuerter Oszillator
    • EP1550934A1
    • 2005-07-06
    • EP04030702.7
    • 2004-12-23
    • TERADYNE, INC.
    • Reichert, Peter
    • G06F1/03
    • G06F1/0328
    • A numeric counter oscillator is disclosed comprising a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output. The output is adapted for transmitting an output value OUT representing an accumulated quotient sum. The multi-bit output increments by a predetermined amount in response to each reference clock period. The remainder accumulator comprises programmable inputs for receiving respective REMAINDER and DIVISOR values, a a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output. The comparator is operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output reaches the predefined integer value.
    • 公开了一种数字计数器振荡器,其包括商累加器和余数累加器。 商累加器具有用于接收QUOTIENT值的可编程输入,参考时钟输入和多位输出。 该输出适于发送表示累积商数的输出值OUT。 响应于每个参考时钟周期,多位输出增加预定量。 剩余累加器包括可编程输入,用于接收相应的REMAINDER和DIVISOR值,参考时钟输入和表示累积数字余数和小于预定数字整数的多位输出。 剩余累加器还包括具有用于接收编程除数值的第一输入的比较器,以及用于接收剩余累加器多位输出的第二输入。 当余数多位输出达到预定义的整数值时,比较器可操作地产生用于应用于商累加器的递增进位信号。