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1. 发明公开

EP1944795A2 Use of F-based gate etch to passivate the high-K/metal gate stack for deep submicron transistor technologies 审中-公开
标题翻译：使用基于F-栅极蚀刻到高K /金属栅极为深亚微米晶体管技术栈的钝化
公开(公告)号：EP1944795A2
公开(公告)日：2008-07-16
申请号：EP08150161.1
申请日：2008-01-10
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) , Katholieke Universiteit Leuven
发明人： Collaert, Nadine , Zimmerman, Paul , Demand, Marc , Boullart, Werner , Shickova, Adelina K.
IPC分类号： H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/28247 , H01L21/3105 , H01L21/32136 , H01L29/4958 , H01L29/4966 , H01L29/4975 , H01L29/66795 , H01L29/785
摘要： A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF 6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better V th control and increased drive current on MuGFET devices is achieved.
摘要翻译：引入氟成一个新的，有效的和成本有效的方法的Hf为主平面或多栅极器件（的MuGFET）的电介质的栅叠层，在负和正偏压温度不稳定性（NBTI和PBTI）一个显著改善所得提供，用于引入氟的，基于SF6金属栅极蚀刻化学的新方法使用的标准处理流程内的热预算之后，导致界面的优良钝化˚F。该方法的主要优点是没有它使用与F引入金属栅极蚀刻，无需额外的植入或治疗。除了显著改善BTI与新颖的方法，更好的V th时的控制和增加的驱动电流上的MuGFET器件得以实现。

2. 发明公开

EP1886318A1 METHOD FOR CONTROLLING THE "FIRST-TO-MELT" REGION IN A PCM CELL AND DEVICES OBTAINED THEREOF 有权转让
标题翻译：方法PCM单元的第一封一系列规则，因此生产的设备
公开(公告)号：EP1886318A1
公开(公告)日：2008-02-13
申请号：EP06744975.1
申请日：2006-05-18
申请人： Koninklijke Philips Electronics N.V. , Interuniversitair Microelektronica Centrum vzw ( IMEC)
发明人： WOUTERS, Dirk, Philips I.P. & Standards , GOUX, Ludovic, Philips I.P. & Standards , LISONI, Judith, Philips I.P. & Standards , GILLE, Thomas, Philips I.P. & Standards
IPC分类号： G11C16/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1226 , H01L45/144 , H01L45/165 , H01L45/1675
摘要： A phase-change-material memory cell is provided. The cell comprises at least one patterned layer of a phase-change material, and is characterized in that this patterned layer comprises at least two regions having different resistivities. If the resistivity of the phase-change material is higher in a well- defined area with limited dimensions ('hot spot') than outside this area, then, for a given current flow between the electrodes, advantageously more Joule heat will be generated within this area compared to the area of the phase- change material where the resistivity is lower.

3. 发明公开

EP1873924A1 Method for determining a pulse position in a signal 审中-公开
标题翻译： Verfahren zur Bestimmung der Position eines einem Signal in einem Signal
公开(公告)号：EP1873924A1
公开(公告)日：2008-01-02
申请号：EP07110972.2
申请日：2007-06-25
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC)
发明人： Desset, Claude , Badaroglu, Mustafa
IPC分类号： H04B1/69
CPC分类号： H04B1/7176 , H04B1/7093 , H04B1/7183 , H04B2201/7071
摘要： A method is presented for determining an actual pulse position in a signal. This signal comprises a plurality of successive frames, wherein each frame has length L and contains one pulse with width W, a number of discrete possible pulse positions being considered within in each frame which is at least L/W. The method comprises the steps of a) sampling the signal at a sampling rate below L/W with a varying sampling phase such that the whole frame length L is covered, b) obtaining a set of samples with at least one at each of the possible pulse positions, c) correlating this set of samples with a set of one or more predetermined values and d) determining the actual pulse position from said correlation. The method provides a low-complex signal acquisition solution in a receiver. In particular, the invention is useful for low-complexity and low-power IR-UWB transceivers.
摘要翻译：提出了一种用于确定信号中的实际脉冲位置的方法。该信号包括多个连续的帧，其中每个帧具有长度L并且包含一个具有宽度W的脉冲，在每个帧内考虑至少为L / W的离散可能脉冲位置的数目。该方法包括以下步骤：a）采用变化的采样相位以低于L / W的采样速率对信号进行采样，使得整个帧长度L被覆盖，b）获得一组采样中的每一个可能的样本脉冲位置，c）将该组样本与一组一个或多个预定值相关联，以及d）从所述相关确定实际脉冲位置。该方法在接收机中提供了低复杂的信号采集解决方案。特别地，本发明对于低复杂度和低功率IR-UWB收发器是有用的。

4. 发明公开

EP1722404A3 Low work function metal alloy 审中-公开
标题翻译：具有低功函数金属合金
公开(公告)号：EP1722404A3
公开(公告)日：2007-08-15
申请号：EP06113814.5
申请日：2006-05-11
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) , NATIONAL UNIVERSITY OF SINGAPORE , Texas Instruments Incorporated
发明人： Yu, HongYu , Jingde, Chen , Mingfu, Li , Kwong, Dim-Lee , Biesemans, Serge , Kittl, Jorge Adrian
IPC分类号： H01L21/28 , H01L29/49 , H01L21/265
CPC分类号： H01L21/26506 , H01L21/28052 , H01L21/28097 , H01L29/4975 , H01L29/517 , H01L29/785
摘要： The present invention discloses low work function metals for use as gate electrode in nMOS devices.
An alloy of lanthanide(s), metal and semiconductor is provided. In particular an alloy of Nickel-Ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting Nickel-Ytterbium-Silicon gate electrode has a work function of about 4.22eV.

5. 发明公开

EP1704638A2 TUNEABLE SPIN TORQUE DEVICE FOR GENERATING AN OSCILLATING SIGNAL AND METHOD FOR TUNING 有权
标题翻译：可调SPIN扭矩装置用于产生信号和摆动调整
公开(公告)号：EP1704638A2
公开(公告)日：2006-09-27
申请号：EP04816313.3
申请日：2004-12-24
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC)
发明人： EYCKMANS, Wouter , LAGAE, Liesbet
IPC分类号： H03B9/14 , H03B5/40 , H01L41/00 , G10K11/36 , G01R33/02 , H03H9/42 , H03H9/64
CPC分类号： G01R33/02 , B82Y25/00 , G11C11/161 , G11C11/1673 , G11C11/1675 , H01F10/193 , H01F10/26 , H01F10/3213 , H01F10/3254 , H01F10/3268 , H01L43/08 , H03B15/006 , H03H2/001 , H03H9/02574 , H03H9/02645 , H03H9/02976 , H03H9/135 , H03H9/6486 , H03K19/19
摘要： The present invention is related to a a device and corresponding methods for generating an oscillating signal. The device comprises a means for providing a current of spin polarised charge carriers, a magnetic, e.g. ferromagnetic, excitable layer adapted for receiving the generated current of spin polarised charge carriers thus generating an oscillating signal with a frequency vosc and an integrated means for interacting with said magnetic, e.g. ferromagnetic, excitable layer such that a selection of said oscillation frequency is achieved. No external field needs to be applied to select or tune the frequency. Different types of integrated means can be used, such as e.g. means inducing mechanical stress in the magnetic, e.g. ferromagnetic, excitable layer, means inducing exchange bias interactions and means inducing magnetostatic interactions.

6. 发明公开

EP1605517A8 Insulating barrier 有权
标题翻译：绝缘屏障
公开(公告)号：EP1605517A8
公开(公告)日：2006-07-05
申请号：EP05108290.7
申请日：2001-10-19
申请人： Interuniversitair Microelektronica Centrum vzw ( IMEC)
发明人： Blomme, Pieter , Govoreanu, Bogdan , Rosmeulen, Maarten
IPC分类号： H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L29/513 , B82Y10/00 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7885
摘要： An insulating barrier (20) extending between a first region (21) and a second region (25), the first region being a layer of localised charge storage sites and the second region being a charge supply region or vice versa, the insulating barrier (20) being provided for tunnelling charge carriers from the first (21) to the second region (25), the insulating barrier (20) comprising a first portion (22) contacting the first region (21) and a second portion (23) contacting the first portion (22) and extending towards the second region (25), the first portion (22) being substantially thinner than the second portion (23), the first portion (22) being constructed in a first dielectric and the second portion (23) being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
摘要翻译：在第一区域（21）和第二区域（25）之间延伸的绝缘阻挡层（20），第一区域是一层局部电荷存储位置，第二区域是电荷供给区域，反之亦然，绝缘阻挡层所述绝缘屏障包括与所述第一区域接触的第一部分和与所述第二区域接触的第二部分，所述第二部分接触所述第二区域，所述第一部分（22）并且朝向所述第二区域（25）延伸，所述第一部分（22）基本上比所述第二部分（23）更薄，所述第一部分（22）被构造成第一电介质并且所述第二部分 23）被构造在与第一电介质不同的第二电介质中，第一电介质具有比第二电介质低的介电常数。

7. 发明授权

EP1902518B1 VOLTAGE CONTROLLED OSCILLATOR WITH SIMULTANEOUS SWITCHING OF FREQUENCY BAND, OSCILLATION CORE AND VARACTOR SIZE 有权转让
标题翻译：与频段的同时改变，和OSZILLATIONSKERNVARACTORGRÖSSE的电压控制振荡器
公开(公告)号：EP1902518B1
公开(公告)日：2009-07-08
申请号：EP06763869.2
申请日：2006-06-23
申请人： Interuniversitair Microelektronica Centrum vzw (IMEC) , Samsung Electronics Co., Ltd.
发明人： CRANINCKX, Jan , HAUSPIE, Dries , KUHNERT, Holger
IPC分类号： H03B5/12
CPC分类号： H03B5/1215 , H03B5/1253 , H03B5/1265 , H03B5/1293
摘要： The invention relates to a voltage controlled oscillator for generating a variable frequency. The oscillator comprises an oscillator core and a transconductive portion for compensating current losses in the oscillator core. The oscillator core comprises an inductive portion with at least one inductive element and a capacitive portion whose capacitance can be continuously varied by means of a control voltage for varying said frequency. The capacitive portion comprises multiple variable capacitive elements whose capacitance is continuously variable by means of said control voltage, each variable capacitive element being switchable for being added to or removed from the capacitive portion.

8. 发明公开

EP2073267A1 Method of fabricating multi-gate semiconductor devices and devices obtained 审中-公开
标题翻译：一种用于制造具有多个栅极的半导体器件和用该方法的装置形成的工艺
公开(公告)号：EP2073267A1
公开(公告)日：2009-06-24
申请号：EP08153677.3
申请日：2008-03-29
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC)
发明人： Jakschik, Stefan , Collaert, Nadine
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66787 , H01L29/78684
摘要： The present invention relates to a method to enhance the mobility in a multi-gate device by combining an increased mobility for the p-type multi-gate device transistor with an increased mobility for the n-type multi-gate device transistor.
It is an advantage of certain aspects of the present invention that both the mobility of a first fin and the mobility of a second fin may be enhanced. It is an advantage of certain aspects of the present invention that the mobility of a first active region with a first fin may be enhanced without degradation of the mobility of a second active region with a second fin. It is another advantage of certain aspects of the present invention that at least a first fin and at least a second fin may be fabricated starting from a substrate, the substrate comprising at least two semiconductor layers wherein the semiconductor layers have different carrier mobility enhancing parameters.
The carrier mobility enhancing parameters can be created by any of a crystalline orientation or a crystalline direction or a semiconductor material or a stress or a combination thereof.
摘要翻译：本发明涉及一种方法，通过在提高的迁移率与在流动性增加组合为p型多栅晶体管器件为n型多栅晶体管器件，以提高在多栅极器件的迁移率。它是本发明的某些方面的优点并一个第一散热片和第二散热片的移动性的两个移动性可以被增强。它是本发明的某些方面的优点也与第一鳍的第一有源区的迁移率可以在没有第二有源区的与第二散热片的流动性的劣化被增强。它是本发明的某些方面的另一个优势并至少一个第一散热片和至少一个第二翼片可以从衬底开始制造，所述基底包括至少两个半导体层worin半导体层具有不同的载流子迁移率增强参数。载流子迁移率增强参数可以通过任何一个晶体取向或结晶方向或半导体材料或应力或它们的组合来创建。

9. 发明公开

EP2073256A1 Method for fabricating a semiconductor device and the semiconductor device made thereof 审中-公开
标题翻译：一种用于生产由一种半导体器件以及半导体器件的工艺
公开(公告)号：EP2073256A1
公开(公告)日：2009-06-24
申请号：EP08153499.2
申请日：2008-03-28
申请人： Interuniversitair Microelektronica Centrum vzw (IMEC) , STMicroelectronics (Crolles 2) SAS
发明人： Lenoble, Damien , Rooyackers, Rita
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L21/26506 , H01L21/26586 , H01L29/66795 , H01L29/7854
摘要： The present invention is related to a method for fabricating a semiconductor device, said method comprising the following subsequent steps:
- providing a substrate comprising a semiconductor material,
- patterning at least one fin in said substrate, said fin comprising a top surface, at least one sidewall surface, and at least one corner,
- creating a supersaturation of point defects in the at least one fin, then
- annealing and subsequently cooling down the at least one fin such that semiconductor atoms of the semiconductor material migrate via the point defects.
摘要翻译：本发明涉及一种用于制造半导体器件的方法，所述方法包括下列连续步骤： - 提供一基板，其包括半导体材料， - 图案化在所说基片的至少一个翼片，所述鳍状物包括顶面，至少，一个侧壁表面上，并且至少一个角部， - 创建点缺陷的在所述至少一个鳍片，然后过饱和 - 退火并随后冷却所述至少一个翅片搜索那样的半导体材料的半导体原子经由点缺陷迁移。

10. 发明公开

EP1969619A1 A METHOD FOR FABRICATING A HIGH-K DIELECTRIC LAYER 审中-公开
标题翻译：方法制备介电层高钾
公开(公告)号：EP1969619A1
公开(公告)日：2008-09-17
申请号：EP06822407.0
申请日：2006-10-20
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： RAGNARSSON, Lars-Ake , ZIMMERMAN, Paul , YAMAMOTO, Kazuhiko , SCHRAM, Tom , DEWEERD, Wim , BRUNCO, David , DE GENDT, Stefan , VANDERVORST, Wilfried
IPC分类号： H01L21/316 , H01L21/311
CPC分类号： H01L21/316 , C23C16/56 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/31122 , H01L21/31604 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus 10%. In a next step, the method according to the present invention comprises thinning the high-k dielectric layer to a second thickness. The present invention also provides a semiconductor device comprising a high-k dielectric layer as fabricated by the method according to embodiments of the present invention.

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