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    • 1. 发明公开
    • Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
    • Getarnter数字家Schaltkreis mit Transistorgeometrie und Kanalunterbrechungen gegen'Reverse Engineering'
    • EP0764985A3
    • 1999-11-17
    • EP96107428.3
    • 1996-05-10
    • Hughes Aircraft Company
    • Baukus, James P.Chow, Lap-WaiClark, William M.Jr.
    • H01L27/02
    • H01L23/573G11C7/24H01L27/02H01L2924/0002H01L2924/00
    • An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity (2, 4, 6, 30; 12, 14, 16, 32) with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants (C) in the substrate (38) rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops (CSO) so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads (8, 18, 28, 34) over the transistor array, with a uniform pattern of heavily doped implant taps (ST, DT) from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.
    • 集成数字电路通过制造具有通用尺寸和几何布局的类似导电性的所有晶体管(2,4,6,3,30; 12,14,16,32)来保护免受逆向工程,为不同的逻辑单元提供通用布局, 将类似导电性的掺杂电路元件与衬底(38)中的导电掺杂植入物(C)连接,而不是金属化互连,并且提供由不可识别的通道停止(CSO)中断的非功能性视在互连,使得所有细胞都是错误的 似乎有一个共同的互连方案。 通过在晶体管阵列上提供均匀图案的金属引线(8,18,28,34)来增强伪装,其中晶体管具有用于连接到引线的重掺杂注入阱(ST,DT)的均匀图案; 通道停止阻塞不需要的抽头引线连接。