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81. 发明公开

EP0438047A1 Microwave FET 失效
标题翻译： FET-Mikrowelle。
公开(公告)号：EP0438047A1
公开(公告)日：1991-07-24
申请号：EP91100005.7
申请日：1991-01-02
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Shiga, Nobuo, c/o Yokohama Works
IPC分类号： H01L29/41 , H01L29/812
CPC分类号： H03D7/125 , H01L29/42316 , H01L29/8124
摘要： In a dual gate FET of this invention, the number of points (A, B, C) for supplying signals to a first gate electrode (20) and the number of points (A', B', C') for supplying signals to a second gate electrode (30) are set to be optimal values so that a noise index is minimized. A difference in electrical length between each signal supply point of each of the first and second gate electrodes (20, 30) and the corresponding gate input terminals (22, 32) has a negligible magnitude with respect to a quarter wavelength of an input signal applied to the corresponding gate input terminal (22, 32). The dual gate FET has a low-noise arrangement, and a microwave can be applied to either one of the first and second gate electrodes (20, 30), thereby obtaining, e. g., a low-noise mixer. In this case, a separator required upon use of a single gate FET can be omitted, thereby easily arranging a monolithic IC.
摘要翻译：在本发明的双栅极FET中，用于向第一栅电极（20）提供信号的点数（A，B，C）和用于提供信号的点数（A'，B'，C'）将第二栅电极（30）设定为最佳值，使得噪声指数最小化。第一和第二栅极电极（20,30）和对应的栅极输入端子（22,32）中的每个信号提供点之间的电长度差异相对于施加的输入信号的四分之一波长具有可忽略的幅度到相应的门输入端（22,32）。双栅极FET具有低噪声布置，并且可以将微波施加到第一和第二栅极电极（20,30）中的任一个，从而获得，例如，例如，低噪声混频器。在这种情况下，可以省略使用单个栅极FET所需的隔板，从而容易地布置单片IC。

82. 发明公开

EP0345380A3 Manufacture of a semiconductor device 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：EP0345380A3
公开(公告)日：1990-07-11
申请号：EP88116864.5
申请日：1988-10-11
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Harada, Masana c/o Mitsubishi Denki K.K.
IPC分类号： H01L29/41 , H01L29/06 , H01L29/78 , H01L21/28
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/4236
摘要： Floating well regions (10) are provided just under trenches in which buried gates (5) are formed. The floating well regions (10) moderate an electric field concentration in the vicinity of the corner and bottom portions of the trenches, in the OFF state of the semiconductor device.

83. 发明公开

EP0322161A3 Silicon carbide barrier between silicon substrate and metal layer 失效
标题翻译：硅衬底和金属层之间的硅碳化物屏障
公开(公告)号：EP0322161A3
公开(公告)日：1990-01-17
申请号：EP88311912.5
申请日：1988-12-16
申请人： FUJITSU LIMITED
发明人： Furumura, Yuji , Mieno, Fumitake , Eshita, Takashi , Itoh, Kikuo , Doki, Masahiko
IPC分类号： H01L29/41 , H01L29/24
CPC分类号： H01L29/456
摘要： An excellent barrier layer (13A, 13B) can be formed by silicon carbide between a silicon substrate (11) or layer and a metal layer because silicon carbide has many properties similar to those of silicon, has a very slow diffusion rate of a metal through the silicon carbide, or prevents a diffusion of a metal into the silicon, and can be deposited by CVD which has an advantage of a good coverage over a step portion such as a contact window.

84. 发明公开

EP0329569A2 Semiconductor device with a thin insulating film 失效
标题翻译： Halbleiteranordnung mit einerdünnenisolierenden Schicht。
公开(公告)号：EP0329569A2
公开(公告)日：1989-08-23
申请号：EP89400463.9
申请日：1989-02-17
申请人： FUJITSU LIMITED
发明人： Ema, Taiji , Shirai, Kazunari
IPC分类号： H01L29/41 , H01L27/10
CPC分类号： H01L28/40 , H01L23/53271 , H01L27/10808 , H01L27/10852 , H01L29/4232 , H01L29/43 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises :
a insulating film (26, 25) having first part (26) and a second part (25), the second part (25) being thinner than the first part (26); and a polycrystalline silicon film having a first part (23) arranged over the first part (26) of the insulating film and a second part (24) arranged over the second part (25) of the insulating film, the second part (24) of the polycrystalline silicon film having a lower concentration of impurities than that of the first part of polycrystalline silicon film.
摘要翻译：半导体器件包括：具有第一部分（26）和第二部分（25）的绝缘膜（26,25），所述第二部分（25）比所述第一部分（26）更薄; 和具有布置在绝缘膜的第一部分（26）上的第一部分（23）和布置在绝缘膜的第二部分（25）上的第二部分（24）的多晶硅膜，第二部分（24）的多晶硅膜具有比第一部分多晶硅膜低的杂质浓度。

85. 发明公开

EP0287031A2 High breakdown voltage insulating film provided between polysilicon layers 失效
标题翻译：高击穿电压包括位于所述多晶硅层之间的绝缘层。
公开(公告)号：EP0287031A2
公开(公告)日：1988-10-19
申请号：EP88105805.1
申请日：1988-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Mikata, Yuuichi c/o Patent Division , Ishihara, Katsunori
IPC分类号： H01L29/41 , H01L21/28
CPC分类号： H01L21/28273 , H01L29/43 , H01L29/4925
摘要： A poly-Si film (53, 54, 55) is formed on a first insulating film (52) overlying a semiconductor substrate (51). A second insulating film (56) is formed on the poly-Si film (53, 54, 55). The poly-Si film (53, 54, 55) comprises a layered structure of a non-single crystal silicon film (53) having a phosphorus concentration of less than 5 × 10²⁰ cm⁻³ or containing no phosphor, a poly-Si film (54) having a phosphorus concentration of over 5 × 10²⁰ cm⁻³ and a poly-Si film (55) containing a phosphorus concentration of over 5 × 10²⁰ cm⁻³ or containing no phosphorus. Since non-single crystal silicon film (53) adjacent to the first insulating film (52) and poly-Si film (55) adjacent to the second insulating film (56) are made lower in their phosphorus concentration, the phosphorus in the films (53) and (55) are not diffused toward the insulating films (53) and (56), respectively. It is thus possible to improve the breakdown voltage across the first and second insulating films.
摘要翻译：多晶Si膜（53，54，55）形成在覆盖半导体衬底（51）的第一绝缘膜（52）。的第二绝缘膜（56）是形成在多晶硅薄膜（53，54，55）。多晶Si膜（53，54，55）包括一个非单晶硅成膜的具有小于5×10 <2> <0>厘米的磷浓度的层状结构（53）< - > <3> 或不含有磷，多晶Si薄膜（54），其具有的磷浓度在5×10 <2> <0>厘米< - > <3>和多晶Si膜（55）含有在磷浓度 5×10 <2> <0>厘米< - > <3>或不含磷。由于非单晶硅膜（53）相邻的第一绝缘膜（52）和多晶硅膜（55）相邻的第二绝缘膜（56）在它们的磷浓度变得更低，磷的膜（ 53）和（55）不朝向分别在绝缘膜（53）和（56），扩散。因此，可以改善在第一和第二绝缘薄膜的击穿电压。

87. 发明公开

EP4354511A2 DEVICE WITH FIELD PLATES 审中-公开
公开(公告)号：EP4354511A2
公开(公告)日：2024-04-17
申请号：EP23195277.1
申请日：2023-09-05
申请人： GlobalFoundries U.S. Inc.
发明人： ZIERAK, Michael J. , BENTLEY, Steven J. , SHARMA, Santosh , LEVY, Mark D. , KANTAROVSKY, Johnatan A.
IPC分类号： H01L29/41 , H01L29/10 , H01L29/20 , H01L29/778
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/404 , H01L29/402 , H01L29/1066
摘要： A structure includes at least one gate structure (20, 22, 38) over semiconductor material (16), the at least one gate structure comprising an active layer (20), a gate metal (38) extending from the active layer and a sidewall spacer (34) on sidewalls of the gate metal; and a field plate (26) aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.

88. 发明公开

EP4273936A1 TRANSISTOR WITH DIELECTRIC SPACERS AND METHOD OF FABRICATION THEREFOR 审中-实审
公开(公告)号：EP4273936A1
公开(公告)日：2023-11-08
申请号：EP23168436.6
申请日：2023-04-18
申请人： NXP USA, Inc.
发明人： Hill, Darrell Glenn
IPC分类号： H01L29/778 , H01L21/338 , H01L29/41 , H01L29/423 , H01L29/417 , H01L29/20
摘要： A transistor device includes a semiconductor substrate (110) and a gate structure (128) formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack (116, 118, 122) over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls (124) in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers (126) may be similarly formed in a field plate channel prior to formation of a field plate (132) of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.

89. 发明公开

EP4266374A1 HIGH-ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME 审中-实审
公开(公告)号：EP4266374A1
公开(公告)日：2023-10-25
申请号：EP22178125.5
申请日：2022-06-09
申请人： United Microelectronics Corp.
发明人： LIN, Jian-Li , CHEN, Cheng-Guo , LO, Ta-Kang , WU, Cheng-Han
IPC分类号： H01L29/778 , H01L29/41 , H01L29/10 , H01L29/417 , H01L29/20
摘要： A high-electron mobility transistor includes a substrate (110), a gate electrode (122), a drain electrode (124), a source electrode (126) and a first field plate (128). The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

90. 发明授权

EP3540784B1 SCHOTTKY BARRIER DIODE AND ELECTRONIC CIRCUIT PROVIDED WITH SAME 有权
公开(公告)号：EP3540784B1
公开(公告)日：2023-08-16
申请号：EP17869159.8
申请日：2017-09-11
发明人： HIRABAYASHI, Jun , MATSUO, Yutaka , FUJITA, Minoru , ARIMA, Jun
IPC分类号： H01L29/872 , H01L21/28 , H01L29/41 , H01L29/47 , H01L29/06 , H01L29/24 , H01L29/417

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