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1. 发明公开

EP0287031A2 High breakdown voltage insulating film provided between polysilicon layers 失效
标题翻译：高击穿电压包括位于所述多晶硅层之间的绝缘层。
公开(公告)号：EP0287031A2
公开(公告)日：1988-10-19
申请号：EP88105805.1
申请日：1988-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Mikata, Yuuichi c/o Patent Division , Ishihara, Katsunori
IPC分类号： H01L29/41 , H01L21/28
CPC分类号： H01L21/28273 , H01L29/43 , H01L29/4925
摘要： A poly-Si film (53, 54, 55) is formed on a first insulating film (52) overlying a semiconductor substrate (51). A second insulating film (56) is formed on the poly-Si film (53, 54, 55). The poly-Si film (53, 54, 55) comprises a layered structure of a non-single crystal silicon film (53) having a phosphorus concentration of less than 5 × 10²⁰ cm⁻³ or containing no phosphor, a poly-Si film (54) having a phosphorus concentration of over 5 × 10²⁰ cm⁻³ and a poly-Si film (55) containing a phosphorus concentration of over 5 × 10²⁰ cm⁻³ or containing no phosphorus. Since non-single crystal silicon film (53) adjacent to the first insulating film (52) and poly-Si film (55) adjacent to the second insulating film (56) are made lower in their phosphorus concentration, the phosphorus in the films (53) and (55) are not diffused toward the insulating films (53) and (56), respectively. It is thus possible to improve the breakdown voltage across the first and second insulating films.
摘要翻译：多晶Si膜（53，54，55）形成在覆盖半导体衬底（51）的第一绝缘膜（52）。的第二绝缘膜（56）是形成在多晶硅薄膜（53，54，55）。多晶Si膜（53，54，55）包括一个非单晶硅成膜的具有小于5×10 <2> <0>厘米的磷浓度的层状结构（53）< - > <3> 或不含有磷，多晶Si薄膜（54），其具有的磷浓度在5×10 <2> <0>厘米< - > <3>和多晶Si膜（55）含有在磷浓度 5×10 <2> <0>厘米< - > <3>或不含磷。由于非单晶硅膜（53）相邻的第一绝缘膜（52）和多晶硅膜（55）相邻的第二绝缘膜（56）在它们的磷浓度变得更低，磷的膜（ 53）和（55）不朝向分别在绝缘膜（53）和（56），扩散。因此，可以改善在第一和第二绝缘薄膜的击穿电压。

2. 发明公开

EP0287931A3 Semiconductor device comprising an electrode having a composite structure 失效
标题翻译：包含具有复合结构的电极的半导体器件
公开(公告)号：EP0287931A3
公开(公告)日：1989-11-02
申请号：EP88105804.4
申请日：1988-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Mikata, Yuuichi c/o Patent Division , Ishihara, Katsunori 501 Mansion-chojamachi , Usami, Toshiro c/o Patent Division
IPC分类号： H01L29/62 , H01L21/28 , H01L29/78 , H01L29/40
CPC分类号： H01L29/66575 , H01L29/43 , H01L29/4925 , H01L29/4933
摘要： A semiconductor device includes a semiconductor substrate (51) having a main surface, and a laminated structure (54). The laminated structure (54) is made up of a nonmonocrystalline silicon layer (54a) and a layer (54b) of refractory metal or refractory metal silicide, formed on the nonmonocrystalline silicon layer (54a), and formed on the main surface of the semiconductor substrate (51). The resistivity of the nonmonocrystalline silicon layer (54a) is set at less than substantially 1 × 10⁻³ Ω· cm by doping an impurity thereinto at the time of deposition of the nonmonocrystalline silicon layer.

3. 发明公开

EP0287931A2 Semiconductor device comprising an electrode having a composite structure 失效
标题翻译： Halbleiteranordnung mit einer Elektrode，die eine gemischte Struktur aufweist。
公开(公告)号：EP0287931A2
公开(公告)日：1988-10-26
申请号：EP88105804.4
申请日：1988-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Mikata, Yuuichi c/o Patent Division , Ishihara, Katsunori 501 Mansion-chojamachi , Usami, Toshiro c/o Patent Division
IPC分类号： H01L29/62 , H01L21/28 , H01L29/78 , H01L29/40
CPC分类号： H01L29/66575 , H01L29/43 , H01L29/4925 , H01L29/4933
摘要： A semiconductor device includes a semiconductor substrate (51) having a main surface, and a laminated structure (54). The laminated structure (54) is made up of a nonmonocrystalline silicon layer (54a) and a layer (54b) of refractory metal or refractory metal silicide, formed on the nonmonocrystalline silicon layer (54a), and formed on the main surface of the semiconductor substrate (51). The resistivity of the nonmonocrystalline silicon layer (54a) is set at less than substantially 1 × 10⁻³ Ω· cm by doping an impurity thereinto at the time of deposition of the nonmonocrystalline silicon layer.
摘要翻译：半导体器件包括具有主表面的半导体衬底（51）和层叠结构（54）。叠层结构（54）由非单晶硅层（54a）和形成在非单晶硅层（54a）上的难熔金属或难熔金属硅化物层（54b）组成，并形成在半导体的主表面上基板（51）。非单晶硅层（54a）的电阻率设定为小于基本上1×10 -3欧米茄。在非单晶硅层沉积时掺杂杂质。

4. 发明授权

EP0287031B1 High breakdown voltage insulating film provided between polysilicon layers 失效
标题翻译：高击穿电压包括位于所述多晶硅层之间的绝缘层。
公开(公告)号：EP0287031B1
公开(公告)日：1995-02-01
申请号：EP88105805.1
申请日：1988-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Mikata, Yuuichi c/o Patent Division , Ishihara, Katsunori
IPC分类号： H01L29/41 , H01L21/28
CPC分类号： H01L21/28273 , H01L29/43 , H01L29/4925

5. 发明授权

EP0287931B1 Semiconductor device comprising an electrode having a composite structure 失效
标题翻译：一种半导体装置，包括具有混合结构的电极。
公开(公告)号：EP0287931B1
公开(公告)日：1994-07-13
申请号：EP88105804.4
申请日：1988-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Mikata, Yuuichi c/o Patent Division , Ishihara, Katsunori 501 Mansion-chojamachi , Usami, Toshiro c/o Patent Division
IPC分类号： H01L29/62 , H01L21/28 , H01L29/78 , H01L29/40
CPC分类号： H01L29/66575 , H01L29/43 , H01L29/4925 , H01L29/4933

6. 发明公开

EP0287031A3 High breakdown voltage insulating film provided between polysilicon layers 失效
标题翻译：多晶硅层之间提供高电压绝缘膜
公开(公告)号：EP0287031A3
公开(公告)日：1989-09-20
申请号：EP88105805.1
申请日：1988-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Mikata, Yuuichi c/o Patent Division , Ishihara, Katsunori
IPC分类号： H01L29/41 , H01L21/28
CPC分类号： H01L21/28273 , H01L29/43 , H01L29/4925
摘要： A poly-Si film (53, 54, 55) is formed on a first insulating film (52) overlying a semiconductor substrate (51). A second insulating film (56) is formed on the poly-Si film (53, 54, 55). The poly-Si film (53, 54, 55) comprises a layered structure of a non-single crystal silicon film (53) having a phosphorus concentration of less than 5 × 10²⁰ cm⁻³ or containing no phosphor, a poly-Si film (54) having a phosphorus concentration of over 5 × 10²⁰ cm⁻³ and a poly-Si film (55) containing a phosphorus concentration of over 5 × 10²⁰ cm⁻³ or containing no phosphorus. Since non-single crystal silicon film (53) adjacent to the first insulating film (52) and poly-Si film (55) adjacent to the second insulating film (56) are made lower in their phosphorus concentration, the phosphorus in the films (53) and (55) are not diffused toward the insulating films (53) and (56), respectively. It is thus possible to improve the breakdown voltage across the first and second insulating films.

7. 发明公开

EP0274390A3 Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：EP0274390A3
公开(公告)日：1989-03-29
申请号：EP88100116.8
申请日：1988-01-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mikata, Yuuichi c/o Patent Division , Usami, Toshiro c/o Patent Division
IPC分类号： H01L29/788 , H01L21/285 , G11C17/00
CPC分类号： H01L29/7885 , H01L21/28273
摘要： In a semiconductor memory device having a floating gate structure, the floating gate electrode (30) is composed of 2 to 10 silicon grains. With the floating gate electrode, the insulation film (31), formed on the floating gate electrode, can have a high breakdown voltage. In a method of manufacturing a semiconductor memory device having a floating gate structure, an insulation film (23) is formed on the silicon substrate (21), portions of the insulation film which are on the drain and source forming regions of the silicon substrate are removed, and a silicon layer (24a) is formed on the silicon substrate (21) by an epitaxial growth process, constituting a floating gate, composed of 2 to 10 silicon grains. According to the manufacturing method, the insulation film (31) formed on the floating gate electrode can have a high breakdown voltage.
摘要翻译：在具有浮栅结构的半导体存储器件中，浮栅电极（30）由2至10个硅晶粒组成。利用浮栅电极，形成在浮栅电极上的绝缘膜（31）可以具有高击穿电压。在制造具有浮栅结构的半导体存储器件的方法中，在硅衬底（21）上形成绝缘膜（23），绝缘膜的位于硅衬底的漏极和源极形成区域上的部分是通过外延生长工艺在硅衬底（21）上形成硅层（24a），构成由2到10个硅晶粒组成的浮栅。根据该制造方法，形成在浮置栅电极上的绝缘膜（31）可以具有高击穿电压。

8. 发明公开

EP0328060A1 Intrinsic gettering during the manufacture of a semiconductor device 失效
标题翻译： Eigengetterungwährendder Herstellung eines Halbleiterbauelementes。
公开(公告)号：EP0328060A1
公开(公告)日：1989-08-16
申请号：EP89102137.0
申请日：1989-02-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kamijo, Hiroyuki c/o Patent Division , Mikata, Yuuichi c/o Patent Division
IPC分类号： H01L21/322 , H01L21/225
CPC分类号： C07D493/20 , C09B29/363 , G03F7/095 , H01L21/2253 , H01L21/3225 , Y10S438/909
摘要： A method for manufacturing a semiconductor device is disclosed which selectively forms in a one-conductivity type semiconductor device a deep impurity-diffused area at over 1100°C in an H₂ gas atmosphere containing N₂, Ar, Ne, He and a combination thereof.
摘要翻译：公开了一种用于制造半导体器件的方法，其在包含N 2，Ar，Ne，He的H 2气体气氛中，在1100℃以上选择性地形成深度杂质扩散区域的单导电型半导体器件及其组合。

9. 发明公开

EP0274390A2 Semiconductor memory device and method of manufacturing the same 失效
标题翻译： Halbleiterspeicheranordnung und Verfahren zu ihrer Herstellung。
公开(公告)号：EP0274390A2
公开(公告)日：1988-07-13
申请号：EP88100116.8
申请日：1988-01-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mikata, Yuuichi c/o Patent Division , Usami, Toshiro c/o Patent Division
IPC分类号： H01L29/788 , H01L21/285 , G11C17/00
CPC分类号： H01L29/7885 , H01L21/28273
摘要： In a semiconductor memory device having a floating gate structure, the floating gate electrode (30) is composed of 2 to 10 silicon grains. With the floating gate electrode, the insulation film (31), formed on the floating gate electrode, can have a high breakdown voltage. In a method of manufacturing a semiconductor memory device having a floating gate structure, an insulation film (23) is formed on the silicon substrate (21), portions of the insulation film which are on the drain and source forming regions of the silicon substrate are removed, and a silicon layer (24a) is formed on the silicon substrate (21) by an epitaxial growth process, constituting a floating gate, composed of 2 to 10 silicon grains. According to the manufacturing method, the insulation film (31) formed on the floating gate electrode can have a high breakdown voltage.
摘要翻译：在具有浮置栅极结构的半导体存储器件中，浮置栅电极（30）由2至10个硅晶粒构成。利用浮栅电极，形成在浮栅电极上的绝缘膜（31）可以具有高的击穿电压。在制造具有浮动栅极结构的半导体存储器件的方法中，在硅衬底（21）上形成绝缘膜（23），绝缘膜的位于硅衬底的漏极和源极形成区域上的部分是并且通过外延生长工艺在硅衬底（21）上形成硅层（24a），构成由2至10个硅晶粒组成的浮动栅极。根据制造方法，形成在浮栅上的绝缘膜（31）可以具有高的击穿电压。

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