专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明公开

EP1464138A4 METHOD AND APPARATUS FOR SIMPLIFIED AUDIO AUTHENTICATION 审中-公开
标题翻译：方法和装置为简体音效认证
公开(公告)号：EP1464138A4
公开(公告)日：2006-07-26
申请号：EP02798566
申请日：2002-12-19
申请人： QUALCOMM INC
发明人： ROSE GREGORY G , QUICK ROY FRANKLIN JR , GANTMAN ALEXANDER
IPC分类号： G07F7/10 , H04L9/32 , H04L9/00 , G06F1/04 , G06F1/06 , G06F1/08 , H04K1/00
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/346 , G06Q20/3823 , G06Q20/3825 , G06Q20/4014 , G06Q20/40975 , G07F7/1016 , G07F7/1025 , H04L9/32 , H04L9/3226 , H04L9/3247 , H04L2209/80 , H04W12/06 , H04W12/10
摘要： An apparatus and method for authentication having a processor (208) and at least one activator coupled to the processor (208) is claimed. A signature generator is coupled to the processor (208) and capable of generating a secure identifier. An emitter coupled to the signal generator capable of emitting the secure identifier. A receiver receives the emitted secure identifier and verifies that the secure identifier was appropriately transmitted. The public key corresponding to the key identifier transmitted is accessed to determine the validity of the secure identifier using the accessed key and that the time indicated in the received secure identifier is verified to be within acceptable time tolerances.

82. 发明公开

EP1482395A1 Transfer clocks for a multi-channel architecture 有权
标题翻译：在einem Mehrfach-Kanalsystem中的Taktübertragung
公开(公告)号：EP1482395A1
公开(公告)日：2004-12-01
申请号：EP03101576.1
申请日：2003-05-30
申请人： Agilent Technologies, Inc.
发明人： Henkel, Thomas , Killig, Ralf
IPC分类号： G06F1/12 , G06F1/06 , G06F1/08
CPC分类号： G01R31/31922 , G06F1/10
摘要： A multi-channel architecture according to the invention comprises a central facility that is under clock control of a central facility's clock signal, and a central transfer clock generator adapted for deriving a central transfer clock signal from the central facility's clock signal. The multi-channel architecture further comprises a set of n channels, with n being a natural number, wherein each channel is under clock control of one out of a plurality of clock signals. Each of the channels comprises a channel transfer clock generator adapted for deriving a channel transfer clock signal from a clock signal of the respective channel, wherein the central facility's clock signal and the clock signals of the channels comprise at least two different clock signals. The transfer clock period of the central transfer clock signal is substantially equal to each of the transfer clock periods of the channel transfer clock signals.
摘要翻译：该架构具有时钟信号发生器，以从中央控制设备（1）的时钟信号导出中央传输时钟信号。通道中的通道传输时钟发生器导出彼此处于相位关系的通道传输时钟信号。信道信道在信道部分可用时，允许信道以同步的方式将其各自的消息发送到设施。还包括以下独立权利要求：（a）包括多渠道架构的自动化测试设备（b）向中央设施发送消息和命令的方法（c）优选地存储在数据上的软件程序或产品载体，用于执行该方法。

83. 发明公开

EP1464138A1 METHOD AND APPARATUS FOR SIMPLIFIED AUDIO AUTHENTICATION 审中-公开
标题翻译： VERFAHREN UND VORRICHTUNG ZUR VEREINFACHTEN AUDIO-AUTHENTISIERUNG
公开(公告)号：EP1464138A1
公开(公告)日：2004-10-06
申请号：EP02798566.2
申请日：2002-12-19
申请人： Qualcomm, Incorporated
发明人： ROSE, Gregory, G. , QUICK, Roy Franklin, Jr. , GANTMAN, Alexander
IPC分类号： H04L9/00 , H04K1/00 , G06F1/04 , G06F1/06 , G06F1/08
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/346 , G06Q20/3823 , G06Q20/3825 , G06Q20/4014 , G06Q20/40975 , G07F7/1016 , G07F7/1025 , H04L9/32 , H04L9/3226 , H04L9/3247 , H04L2209/80 , H04W12/06 , H04W12/10
摘要： An apparatus and method for authentication having a processor (208) and at least one activator coupled to the processor (208) is claimed. A signature generator is coupled to the processor (208) and capable of generating a secure identifier. An emitter coupled to the signal generator capable of emitting the secure identifier. A receiver receives the emitted secure identifier and verifies that the secure identifier was appropriately transmitted. The public key corresponding to the key identifier transmitted is accessed to determine the validity of the secure identifier using the accessed key and that the time indicated in the received secure identifier is verified to be within acceptable time tolerances.
摘要翻译：要求具有处理器和耦合到处理器的至少一个激活器的认证装置和方法。签名生成器耦合到处理器并且能够生成安全标识符。耦合到能够发出安全标识符的信号发生器的发射器。接收器接收发射的安全标识符，并验证安全标识符是否被适当地发送。访问与发送的密钥标识符相对应的公共密钥，以使用所访问的密钥来确定安全标识符的有效性，并且验证所接收的安全标识符中指示的时间在可接受的时间容限内。

84. 发明公开

EP1166418A4 SLOW RESPONSES IN REDUNDANT ARRAYS OF INEXPENSIVE DISKS 有权
标题翻译： SLOW REAKTIONE期冗余廉价的磁盘矩阵
公开(公告)号：EP1166418A4
公开(公告)日：2002-11-20
申请号：EP00915947
申请日：2000-02-29
申请人： SEACHANGE SYSTEMS INC
发明人： MANN BRUCE E , TRASATTI PHILIP J , YWOSKUS JOHN A
IPC分类号： G06F3/06 , G06F11/10 , G11B20/10 , H02H3/05 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/14 , H03K19/003 , H04B1/74 , H04L1/22 , H04L7/00 , H04N7/173 , H05K10/00
CPC分类号： G06F11/1076 , G06F11/1088
摘要： A redundant array includes a plurality of disks, a bus coupling the disks, a receiving device, and a device to reconstruct a block stored in one of the disks. The device reconstructs the block with associated data and parity blocks from other disks. The device transmits the reconstructed block to the receiving device in response to the one of the disks being slowly responding. A method includes requesting a first disk to transmit a first block, reconstructing, when necessary, the first block from associated data stored in other disks of a RAID configuration, and transmitting the reconstructed block directly to a receiving device. The transmitting is in response to the first disk not transmitting the block in a predetermined time.

85. 发明公开

EP0994405A2 Computer system controlling memory clock signal and method for controlling the same 审中-公开
标题翻译：用于控制其的存储器时钟信号和控制方法的计算机系统
公开(公告)号：EP0994405A2
公开(公告)日：2000-04-19
申请号：EP99307691.8
申请日：1999-09-29
申请人： Samsung Electronics Co., Ltd.
发明人： Lee, Jung-Keun
IPC分类号： G06F1/06
CPC分类号： G06F1/06
摘要： A computer system controlling memory clock signals of a DIMM (dual in-line memory module) socket includes a processor controlling a 66 MHz or a 100 MHz system bus clock signal to be generated, a DIMM memory module supporting the 66 MHz or the 100 MHz system bus clock signal, a clock generator generating the 66 MHz or the 100 MHz system bus clock signal according to control signals from of the processor, a clock buffer, and first and second system controllers. The clock generator and the clock buffer store setting data according to memory data of a memory module from a first system controller. The first and the second system controllers control memory bus clock signals corresponding to an inserted single-sided type or double-sided type DIMM memory module. As a result, clock signals to an unused memory module socket are disabled or unused clock signals of a memory module socket in use are cut off in response to detection of the kind of an inserted memory module.

86. 发明公开

EP0826170A4 METHOD AND APPARATUS FOR ENHANCING PERFORMANCE OF A PROCESSOR 失效
标题翻译：方法和设备用于提高处理器性能
公开(公告)号：EP0826170A4
公开(公告)日：1999-01-20
申请号：EP96923375
申请日：1996-06-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： MOTE L RANDALL JR
IPC分类号： G06F1/00 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/20 , G06F1/26 , G06F1/32 , G06F9/30
CPC分类号： G06F1/26 , G06F1/08 , G06F1/206
摘要： An optimum processing frequency (160) is set for processors based upon the individual operational characteristics of each processor. The source voltage (145) supplied to the processor is increased, manually or under software control, to the maximum value specified for the processor. This allows the processor to operate at the maximum possible frequency. The processor clock frequency (160) is varied with respect to the motherboard clock frequency so that the processor clock can be arbitrarily set to its maximum operational frequency. A method of approximation is used to determine the maximum clock frequency at which the processor will fucntion properly. In order to prevent thermally induced semiconductor breakdown, additional heat sinking is performed and/or a thermal management scheme is used. The supply voltage may also be controlled in conjunction with the clock rate to determine the optimum operating frequency and supply voltage to the processor.

87. 发明公开

EP0886918A2 CLOCK MULTIPLEXER 失效
标题翻译：时钟信号多路复用器
公开(公告)号：EP0886918A2
公开(公告)日：1998-12-30
申请号：EP97913398
申请日：1997-12-08
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： SAMSOM SEBASTIANUS , THIJSSEN ALOYSIUS , BAKER KEITH
IPC分类号： H03K5/00 , G06F1/06 , H03K17/00
CPC分类号： H03K17/002 , G06F1/04
摘要： A circuit includes a plurality of logically identical clock modules which are all capable of driving the same clock output. The circuit has a selection input for selecting one of the clock modules for driving the clock output. After a change of the selection, a clock module just deselected awaits the completion of a period of the own clock signal before switching to deselection. The clock modules have a hold-off input which is coupled to a common signal line. A newly selected clock module switches to a selection state only after a beginning of a period of the own clock signal, provided that the selected clock module previously detects a signal on its hold-off input which indicates that all clock modules have deselected themselves. The common signal line is preferably coupled to the clock output, deselection being detected on the basis of the signal level which occurs after the beginning of the period after a change of the selection.

88. 发明公开

EP0729088A3 Single chip microcomputer having a plurality of timer counters 失效
标题翻译：单片机与许多定时计数器
公开(公告)号：EP0729088A3
公开(公告)日：1998-08-12
申请号：EP96102605
申请日：1996-02-21
申请人： NEC CORP
发明人： SUZUKI KAZUHIKO
IPC分类号： G06F15/78 , G06F1/06 , G06F1/14
CPC分类号： G06F1/14
摘要： In a microcomputer comprising first and second timer counters, an output signal of the first timer counter is supplied through a logic gate to the second timer counter as a clock supply control signal.

89. 发明公开

EP0708398A2 Clock control unit 失效
标题翻译： Taktssteuerungseinheit
公开(公告)号：EP0708398A2
公开(公告)日：1996-04-24
申请号：EP95307372.3
申请日：1995-10-17
申请人： ADVANCED MICRO DEVICES INC.
发明人： Hawkins, Keith G. , Wakeland, Carl K.
IPC分类号： G06F1/06 , G06F1/32
CPC分类号： G06F1/324 , G06F1/06 , G06F1/22 , G06F1/3203 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal. A power management unit is incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions. The pin-count of the integrated processor is finally minimized by allowing the selective multiplexing of certain external pins depending upon the desired functionality of the integrated processor.
摘要翻译：集成处理器在单个单片电路上制造，并采用电路来适应现代PID的数据密集型，视图密集型和语音密集型需求。集成处理器包括CPU内核，存储器控制器和各种外围设备，以实现多功能性和高性能功能。集成处理器通过提供包括用于产生不同频率的时钟信号的多个锁相环的时钟控制单元来消耗更少的功率，以适当地对集成处理器的各个子系统进行时钟。由时钟控制单元提供给各个子系统的时钟信号是从单晶振荡器输入信号导出的。功率管理单元被集成在集成处理器内以控制到各个子系统的某些时钟信号的频率和/或应用，以及控制与功率管理相关的功能。通过允许根据集成处理器的期望功能选择性地复用某些外部引脚，从而最终最小化集成处理器的引脚数。

90. 发明公开

EP0699991A2 Method and apparatus for switching clock signals in a fault-tolerant computer system 失效
标题翻译：方法和装置用于在容错计算机系统中进行切换的时钟信号
公开(公告)号：EP0699991A2
公开(公告)日：1996-03-06
申请号：EP95304733.9
申请日：1995-07-06
申请人： STRATUS COMPUTER, INC.
发明人： Barbera, David R. , Savicki, Franklin M. , Splitz, David E.
IPC分类号： G06F1/06 , G06F1/12
CPC分类号： G06F11/1604 , G06F1/10 , G06F11/1675 , G06F11/20
摘要： The present invention relates to a clock switching circuit (300) which switches between clock signals (BP_4, LOC_32) generated by a local clock unit and those generated by a system clock unit when disabling, and then subsequently enabling, the system clock unit. The clock switching circuit (300) includes a plurality of switching circuits (600, 700, 800) that are arranged and configured to switch between the system and local clock units so as to provide a substantially uninterrupted stream of clock signals (BRD_16, BRD_4) to selected components of a fault-tolerant computer system. This arrangement ensures that information stored on the selected components is not lost during disablement of the system clock unit.
摘要翻译：该电路具有被配置为通过由系统时钟单元产生若干系统时钟信号和逻辑接地信号中的一个向所多路复用的输出线的多路复用器。第二多路复用器被配置成通过由本地时钟单元和逻辑接地信号生成到所述第二多路转换器的输出线几个本地时钟信号中的一个。所述第一和第二多路复用器被配置成进一步的调查做了系统和本地时钟信号通到输出线中的一个。第三多路复用器被布置成接收来自耦合到所述第三多路转换器的输出线的系统和本地时钟信号中的一个。因此，该第三多路复用器通过该系统和本地时钟信号到第三输出线中的一个。时钟控制器基因速率使能信号没有配置所述第三多路复用器以从所述组的输入线的其它的一个切换到其他系统和本地时钟信号的传递到第三输出线，而不的完整性造成不利影响时钟信号通过第三多路转换器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式