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71. 发明公开

EP3002780A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3002780A1
公开(公告)日：2016-04-06
申请号：EP15184691.2
申请日：2015-09-10
申请人： Renesas Electronics Corporation
发明人： KAWASHIMA, Yoshiyuki , YOSHIDA, Shoji
IPC分类号： H01L21/28 , H01L21/02 , H01L21/30 , H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L29/7923 , H01L21/28176 , H01L21/28282 , H01L21/3003 , H01L21/324 , H01L27/11573 , H01L29/513 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and a gate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.

72. 发明公开

EP2867387A4 METHOD FOR USING SPUTTERING TARGET AND METHOD FOR MANUFACTURING OXIDE FILM 审中-公开
标题翻译：使用溅射靶的方法和制造氧化膜的方法
公开(公告)号：EP2867387A4
公开(公告)日：2016-03-09
申请号：EP13810525
申请日：2013-06-17
申请人： SEMICONDUCTOR ENERGY LAB
发明人： YAMAZAKI SHUNPEI
IPC分类号： C23C14/34 , C23C14/08 , C23C14/35 , H01L21/363 , H01L21/8247 , H01L27/115 , H01L51/50 , H05B33/14
CPC分类号： C23C14/3464 , C23C14/08 , C23C14/086 , C23C14/34 , C23C14/3414 , C23C14/352 , C23C14/564 , H01L29/513 , H01L29/517 , H01L29/7869

73. 发明授权

EP1986240B1 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：EP1986240B1
公开(公告)日：2016-03-09
申请号：EP08162077.5
申请日：2003-10-23
申请人： Fujitsu Semiconductor Limited
发明人： Anezaki, Toru, Fujitsu Limited
IPC分类号： H01L29/78 , H01L21/336 , H01L29/788 , H01L29/792 , H01L27/115 , H01L21/8247 , H01L27/088 , H01L21/8234 , H01L21/28 , H01L21/8239 , H01L27/105
CPC分类号： H01L21/823462 , H01L21/2652 , H01L21/28273 , H01L21/28282 , H01L21/823456 , H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11573 , H01L29/4983 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film. The semiconductor device may further comprise second laminated side wall spacers having three or more layers and formed on side walls of a laminated gate electrode structure, the second laminated side wall spacers including a nitride film as an intermediate layer not contacting the semiconductor substrate.

74. 发明公开

EP2745295A4 APPARATUS AND METHODS INCLUDING SOURCE GATES 有权
标题翻译：设备和方法的研究SOURCE GATES
公开(公告)号：EP2745295A4
公开(公告)日：2016-02-24
申请号：EP12824349
申请日：2012-08-14
申请人： MICRON TECHNOLOGY INC
发明人： GODA AKIRA , AHMED SAFQAT , HASNAT KHALED , PARAT KRISHNA K
IPC分类号： G11C16/02 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/0408 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3418 , G11C16/3427 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582
摘要： Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

75. 发明公开

EP2985763A1 SUB-BLOCK ERASE 有权
标题翻译：个子块LÖSCHUNG
公开(公告)号：EP2985763A1
公开(公告)日：2016-02-17
申请号：EP15168157.4
申请日：2015-05-19
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Lue, Hang-Ting , Chang, Kuo-Pin
IPC分类号： G11C16/04 , G11C16/16 , H01L27/115
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/16 , G11C2216/18 , H01L27/11551 , H01L27/11578
摘要： A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.
摘要翻译：提供了一种用于操作包括多个存储单元块的NAND阵列的方法。多个块中的存储单元块包括在第一串选择开关和第二串选择开关之间具有通道线的多个NAND串。多个NAND串在第一和第二串选择开关之间共享一组字线。通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。字线侧擦除电压被施加到所选择的子集，包括由所选块中的NAND串所共享的字线集合中的多于一个成员，以在耦合到所选择的子集的存储器单元中诱发隧道，同时在存储器单元中禁止隧道耦合到未选择的子集，其包括该组字线的多于一个成员。

76. 发明公开

EP2983196A1 A method for manufacturing a floating gate memory element 审中-公开
标题翻译： Verfahren zur Herstellung eines Speeslements mit Schwebegatter
公开(公告)号：EP2983196A1
公开(公告)日：2016-02-10
申请号：EP14180191.0
申请日：2014-08-07
申请人： IMEC VZW
发明人： Blomme, Pieter
IPC分类号： H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L27/11556 , H01L21/02592 , H01L21/02667 , H01L21/28273 , H01L29/42324 , H01L29/42364 , H01L29/66825 , H01L29/7889
摘要： A method for manufacturing a floating gate memory element is disclosed. The method (200) comprising forming (202) a stack of horizontal layers (100) arranged on top of each other, the stack of horizontal layers (100) comprising alternating sacrificial layers of a first type (102) and sacrificial layers of a second type (104); forming (204) a vertical opening (106) through said horizontal stack of layers (100), wherein said vertical opening (106) comprises a sidewall surface (108), forming (206) a first vertical dielectric layer (110) on said sidewall surface (108), forming (208) a vertical floating gate layer (112) on said first vertical dielectric layer (110), forming (210) a second vertical dielectric layer (114) on said vertical floating gate layer (112), filling (211) said vertical opening (106) with a channel material (107), forming (212) cavities of a first type (105) in said sacrificial layers of the second type (104), said cavities (105) being adjacent to said first vertical dielectric layer (110), removing (214) portions of said first vertical dielectric layer (110) and said vertical floating gate layer (112) at locations adjacent to said cavities of the first type (105) thereby extending said cavities of the first type (105) such that said second vertical dielectric layer (114) is exposed, filling (216) said extended cavities of the first type (105) with an isolating material (116), forming (218) cavities of a second type (117) in said sacrificial layers of the first type (102), said cavities of the second type (117) being adjacent to and exposing said first vertical dielectric layer (110), forming (220) a third dielectric layer (118) in said cavities of the second type (117), said third dielectric layer (118) being formed on said first vertical dielectric layer (110), forming (222) a conductive material (120) in said cavities of the second type (117), said conductive material (120) being in contact with said third dielectric layer (118).
摘要翻译：公开了一种用于制造浮动栅极存储元件的方法。所述方法（200）包括形成（202）布置在彼此顶部的水平层（100）的堆叠，所述水平层（100）的堆叠包括第一类型（102）的交替牺牲层和第二类型的牺牲层类型（104）; 通过所述水平叠层（100）形成（204）垂直开口（106），其中所述垂直开口（106）包括侧壁表面（108），在所述侧壁上形成（206）第一垂直介电层（110）在所述第一垂直介质层上形成（208）垂直浮动栅层（112），在所述垂直浮栅（112）上形成（210）第二垂直介电层（114），填充（211），所述垂直开口（106）具有通道材料（107），在所述第二类型（104）的所述牺牲层中形成第一类型（105）的空腔（212），所述空腔（105）邻近所述第一垂直介电层（110），在与第一类型（105）的所述空腔相邻的位置处去除（214）所述第一垂直介电层（110）和所述垂直浮动栅层（112）的部分，从而延伸所述第一垂直介质层第一类型（105），使得所述第二垂直介电层（114）暴露，填充（216）所述第一类型（105）的扩展腔具有隔离材料（116），在所述第一类型（102）的所述牺牲层中形成第二类型（117）的空腔（218），所述第二类型类型（117）与所述第一垂直介电层（110）相邻并暴露，在所述第二类型（117）的所述空腔中形成（220）第三介电层（118），所述第三介电层（118）形成在所述第一垂直介电层（110）在所述第二类型（117）的所述空腔中形成（222）导电材料（120），所述导电材料（120）与所述第三介电层（118）接触。

77. 发明公开

EP2973710A1 FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY 有权
标题翻译：垂直存储器中的浮动门存储器单元
公开(公告)号：EP2973710A1
公开(公告)日：2016-01-20
申请号：EP14770149.4
申请日：2014-03-05
申请人： Micron Technology, Inc.
发明人： DENNISON, Charles H. , GODA, Akira , HOPKINS, John , SIMSEK-EGE, Fatma Arzum , PARAT, Krishna K.
IPC分类号： H01L27/115
摘要： Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
摘要翻译：垂直存储器中的浮动门存储单元。控制栅极形成在第一层介电材料和第二层介电材料之间。在第一层介电材料和第二层介电材料之间形成浮置栅极，其中浮置栅极包括朝控制栅极延伸的突起。电荷阻挡结构形成在浮置栅极和控制栅极之间，其中电荷阻挡结构的至少一部分缠绕突起。

78. 发明公开

EP2973707A1 MEMRISTORS WITH DOPANT-COMPENSATED SWITCHING 审中-公开
标题翻译：具有掺杂剂补偿开关的MEMRISTOR
公开(公告)号：EP2973707A1
公开(公告)日：2016-01-20
申请号：EP13878298.2
申请日：2013-03-13
申请人： Hewlett-Packard Development Company, L.P.
发明人： YANG, Jianhua , ZHANG, Minxian , RIBEIRO, Gilberto Medeiros , WILLIAMS, R. Stanley
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/145 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1641
摘要： A memristor with dopant-compensated switching, the memristor having a bottom electrode, a top electrode, and an active region sandwiched between the bottom electrode and the top electrode. The active region is made up of an electrically insulating material and an electrically conducting material. The insulating material includes compensating dopants to partially or fully compensate for native dopants in the insulating material. Methods for making the memristor are also disclosed.
摘要翻译：具有掺杂剂补偿切换的忆阻器，忆阻器具有底部电极，顶部电极和夹在底部电极和顶部电极之间的有源区。有源区由电绝缘材料和导电材料组成。绝缘材料包括补偿掺杂剂以部分或完全补偿绝缘材料中的天然掺杂剂。还公开了制造忆阻器的方法。

79. 发明公开

EP2960928A1 ULTRAVIOLET-ERASABLE NONVOLATILE SEMICONDUCTOR DEVICE 审中-公开
标题翻译： ULTRAVIOLETT-LÖSCHBARESNICHTFLÜCHTIGESHALBLEITERBAUELEMENT
公开(公告)号：EP2960928A1
公开(公告)日：2015-12-30
申请号：EP14754296.3
申请日：2014-01-22
申请人： Seiko Instruments Inc.
发明人： SOMEYA, Tetsuo
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/768 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L23/3192 , H01L23/53295 , H01L27/1443 , H01L2924/0002 , H01L2924/00
摘要： In order to provide an ultraviolet-erasable nonvolatile semiconductor device that has a high water resistance and is capable of erasing data by ultraviolet rays, a protective film includes a silicon nitride film (12) and a silicon oxynitride film (13). The silicon nitride film (12) and the silicon oxynitride film (13) cooperate to prevent moisture from penetrating into the ultraviolet-erasable nonvolatile semiconductor device. The silicon nitride film 12 has such a thickness with which a time for erasing data in a nonvolatile semiconductor storage element (17) through irradiation of the ultraviolet rays is not increased.
摘要翻译：为了提供具有高耐水性且能够通过紫外线擦除数据的紫外线可擦除的非易失性半导体器件，保护膜包括氮化硅膜（12）和氮氧化硅膜（13）。氮化硅膜（12）和氮氧化硅膜（13）配合，以防止水分渗入紫外线可擦除的非易失性半导体器件。氮化硅膜12具有通过紫外线的照射而擦除非易失性半导体存储元件（17）中的数据的时间的厚度。

80. 发明公开

EP2956963A1 TUNGSTEN SALICIDE GATE SOURCE FOR VERTICAL NAND STRING TO CONTROL ON CURRENT AND CELL PILLAR FABRICATION 有权
标题翻译： WOLFRAMSALIZID门源垂直NANDSTRING用于控制电力和细胞POST PRODUCTION
公开(公告)号：EP2956963A1
公开(公告)日：2015-12-23
申请号：EP14773649.0
申请日：2014-02-13
申请人： Intel Corporation
发明人： SIMSEK-EGE, Fatma A. , PARAT, Krishna K.
IPC分类号： H01L27/115
摘要： A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.

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