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61. 发明授权

EP0361792B1 Semiconductor device having a reverse bias voltage generator 失效
标题翻译：具有反向偏压发生器的半导体器件。
公开(公告)号：EP0361792B1
公开(公告)日：1995-01-18
申请号：EP89309616.4
申请日：1989-09-21
申请人： NEC CORPORATION
发明人： Nakada, Kazuhiro
IPC分类号： H03K19/003
CPC分类号： G05F3/205 , H03K19/00361

62. 发明公开

EP0625824A2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：EP0625824A2
公开(公告)日：1994-11-23
申请号：EP94107486.6
申请日：1994-05-13
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Makino, Eiichi , Koyanagi, Masaru
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： The control voltage φ1 outputted by the control voltage generating circuit (1) is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor (P1), but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage φ1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor (P4) of a low-voltage operating output section (6) operative only at a voltage lower than a predetermined value. The transistor (P2) of a full-voltage operating output section (5) of the output circuit is always operative on the basis of the control signal φH of the data output control circuit (3). When the external supply voltage is low below the predetermined value, the transistor (P4) is perfectly turned on, so that the conductance thereof increases. In the semiconductor integrated circuit device operative on the basis of a plurality of supply voltages, it is possible to prevent the operation margin from being reduced near the switching point of the gate voltages of the driving transistors and the data output transistors.
摘要翻译：在外部电源电压Vcc低于晶体管（P1）的阈值的范围内，由控制电压生成电路（1）输出的控制电压φ1处于低电平，但是当外部电源电压电源电压Vcc升高。在匹配外部电源电压Vcc之后，控制电压φ1以与外部电源电压Vcc相同的方式增加。通过使用具有如上所述的用于输出电路的特性的控制电压，受控制的是低电压操作输出部分（6）的晶体管（P4）的栅极仅在低于预定值的电压下操作。输出电路的全电压操作输出部分（5）的晶体管（P2）总是根据数据输出控制电路（3）的控制信号φH操作。当外部电源电压低于预定值时，晶体管（P4）完全导通，从而其电导增加。在基于多个电源电压工作的半导体集成电路装置中，可以防止在驱动晶体管和数据输出晶体管的栅极电压的切换点附近减小操作余量。

63. 发明公开

EP0608786A1 Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads 失效
标题翻译：非常低的电压CMOS芯片之间逻辑信号的传输的大量的每一个都具有大的电容性负载的高速输出线。
公开(公告)号：EP0608786A1
公开(公告)日：1994-08-03
申请号：EP94100898.9
申请日：1994-01-22
申请人： STANDARD MICROSYSTEMS CORPORATION
发明人： Wanlass, Frank M.
IPC分类号： H03K19/00 , H03K19/003 , H03K19/0185
CPC分类号： H03K3/3565 , H03K17/08142 , H03K17/162 , H03K19/00315 , H03K19/00361 , H03K19/018521 , H03K19/018592
摘要： A CMOS integrated circuit (IC) device embodiment of the present invention comprises an internal logic circuit operating with traditional 3.3 volt or five volt internal logic levels, an output buffer to convert the internal logic levels to external logic levels of 0.3 volts and an input buffer to convert the 0.3 volt external logic levels to the internal logic levels. In a CMOS IC device having numerous external output loads including relatively high capacitive values that are driven at very high clock rates, the restricted voltage swings of the 0.3 volt external logic levels permit unusually large numbers of devices to be driven without exceeding a predetermined power dissipation limit of the CMOS IC device. The low external logic levels further permit electrostatic discharge (ESD) protection to be included on all signal inputs and outputs of the CMOS IC device. The ESD protection comprises a pair of opposite polarity silicon PN junction diodes in parallel and connected between each signal line and a ground reference.

64. 发明授权

EP0292641B1 Output buffer of MOS semiconductor integrated circuit 失效
标题翻译：输出缓冲器，用于MOS半导体集成电路。
公开(公告)号：EP0292641B1
公开(公告)日：1994-05-18
申请号：EP88101710.7
申请日：1988-02-05
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Kinugasa, Masanori c/o Patent Division , Shimazaki, Kenichiro , Tanaka, Fuminari c/o Patent Division
IPC分类号： H01L27/02 , H01L23/52 , H03K19/094
CPC分类号： H03K19/00361 , H01L23/528 , H01L27/11898 , H01L2924/0002 , H03K5/133 , H03K2005/00221 , H01L2924/00

65. 发明公开

EP0591750A2 Verfahren zur Stromeinstellung eines monolithisch integrierten Padtreibers 失效
标题翻译： Verfahren zur Stromeinstellung eines monolithisch integrierten Padtreibers。
公开(公告)号：EP0591750A2
公开(公告)日：1994-04-13
申请号：EP93115154.2
申请日：1993-09-21
申请人： Deutsche ITT Industries GmbH
发明人： Giebel, Burkhard, Dipl.-Ing.
IPC分类号： H03K19/003
CPC分类号： H03K17/166 , H03K19/00361
摘要： Ein Verfahren zur Stromeinstellung zumindestens eines Padtreibers (D; D1, D2, Dn), bei dem durch eine verbesserte Einstellbarkeit des Ausgangsstroms (i1) eines Ausgangstransistors (t1) die störenden Spannungseinbrüche auf den Versorgungsleitungen reduziert werden. Es werden insbesonders die impulsartigen Stromspitzen bei der raschen Umladung hoher Lastkapazitäten (C) vermieden. Hierzu wird in einem ersten bzw. zweiten Bereich (b1, b2) der Ausgangsspannung (u1) der Ausgangstransistor (t1) als stromgesteuertes bzw. spannungsgesteuertes Element betrieben.
摘要翻译：由于输出晶体管的输出电流（i1）的可调整性的改善，用于调节至少一个输出驱动器（D; D1，D2，Dn）的电流的方法，其中干扰电压下降在供电线上（T1）。特别地，避免了在高负载电容（C）的快速再充电期间的脉冲状电流峰值。为此，输出晶体管（t1）在输出电压（u1）的第一或第二范围（b1，b2）中作为电流控制或电压控制元件工作。

66. 发明公开

EP0585505A1 Low noise buffer 失效
标题翻译：流氓mit em Ra chen。
公开(公告)号：EP0585505A1
公开(公告)日：1994-03-09
申请号：EP92830335.3
申请日：1992-06-26
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Maloberti, Franco , Marchesi, Gianmarco , Torelli, Guido
IPC分类号： H03K19/00 , H03K19/003 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051 , H03K19/00361
摘要： The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage between a pre-existent logic level and a different logic level, during a system's "dead" time, with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial charging or discharging of the load capacitance before actually performing a switching, with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.
摘要翻译：在系统的“死区”时间内，通过预充电输出电流脉冲将输出节点“预充电”到预先存在的逻辑电平与不同逻辑电平之间的中间电压，大大降低了由数据输出缓冲器产生的开关噪声在第三时间间隔期间，在第一时间间隔内具有恒定时间导数和在第二时间间隔期间具有相反符号的恒定时间导数，然后在具有恒定时间导数的输出电流执行实际切换之前。在实际进行切换之前，通过受控制的三角形输出电流脉冲对负载电容的部分充电或放电避免了输出电流的任何突然变化，从而限制了开关噪声。本发明的缓冲器在高速存储器件中特别有用。

67. 发明公开

EP0574168A3 High speed CMOS bus driver circuits 失效
标题翻译：高速CMOS总线驱动器电路
公开(公告)号：EP0574168A3
公开(公告)日：1994-02-02
申请号：EP93304166.7
申请日：1993-05-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： A high speed bus driver circuit is disclosed that minimizes output signal oscillation by maintaining the clamp voltage at specified levels. The driver circuit includes a pair of voltage preference circuits that are designed to deliver the appropriate clamp voltages even at the best case speed corners, the circuit prevents simultaneous turn on of drive transistors, equalizes the propagation delay and provides for first access for tri-stating the bus driver transistors.
摘要翻译：公开了一种高速总线驱动器电路，其通过将钳位电压维持在特定的电平来使输出信号振荡最小化。该驱动器电路包括一对电压优先电路，该电路被设计为即使在最佳情况下的速度拐角也提供适当的钳位电压，该电路防止驱动晶体管的同时导通，均衡传播延迟并提供三态总线驱动器晶体管。

68. 发明公开

EP0576204A1 Integrated circuit buffer with controlled rise and fall times 失效
标题翻译： Integrierte Pufferschaltung mit gesteuerten Anstiegs- und Abfallszeiten。
公开(公告)号：EP0576204A1
公开(公告)日：1993-12-29
申请号：EP93304710.2
申请日：1993-06-17
申请人： AT&T Corp.
发明人： Gabara, Thaddeus John
IPC分类号： H03K19/003 , H03K17/14
CPC分类号： H03K17/145 , H03K19/00361
摘要： Process, voltage, and temperature variations affect the noise generation of an output buffer. Controlling the switching speed of the buffer over these variations also controls the buffer noise, which may be due to ground bounce or other reasons. In one prior-art technique, the current flow behavior of a static circuit is used to control the rise and/or fall times of the output buffer. However, accounting for all possible variations in the factors that influence the switching speed is difficult with a static control circuit. In the inventive technique, the AC switching behavior of a scaled-down buffer (201,202) that is driven by a periodic signal (CLOCK) generates the control voltage (VCP). In this manner, the factors that influence buffer switching speed, including process, voltage, and temperature variations, may be more accurately accounted for.
摘要翻译：过程，电压和温度变化影响输出缓冲器的噪声产生。通过这些变化控制缓冲器的切换速度也可以控制缓冲区噪声，这可能是由于地面反弹或其他原因造成的。在一种现有技术中，使用静态电路的电流流动来控制输出缓冲器的上升和/或下降时间。然而，考虑到静态控制电路难以影响开关速度的因素的所有可能的变化。在本发明的技术中，由周期信号（CLOCK）驱动的缩小缓冲器（201,202）的交流切换行为产生控制电压（VCP）。以这种方式，可以更准确地考虑影响缓冲器切换速度的因素，包括处理，电压和温度变化。

69. 发明公开

EP0574184A2 High speed CMOS output buffer circuits 失效
标题翻译： Schnelle CMOS Ausgangspufferschaltungen。
公开(公告)号：EP0574184A2
公开(公告)日：1993-12-15
申请号：EP93304317.6
申请日：1993-06-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Mahmood, Qazi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00361 , H03K17/163
摘要： An output buffer circuit is disclosed that minimizes signal oscillation or ringing on a data bus while limiting the power dissipated. This circuit includes a pair of reference voltage generators which provide damp voltages that limit the signal oscillation and a mechanism for shutting down the appropriate generator when it is not operating. The output buffer circuit has the capability of driving the output resistors to their CMOS levels in order to maximize the sinking and sourcing currents.
摘要翻译：公开了一种输出缓冲器电路，其最小化数据总线上的信号振荡或振铃，同时限制功耗。该电路包括一对参考电压发生器，其提供限制信号振荡的阻尼电压，以及用于当其不工作时关闭适当发电机的机构。输出缓冲电路具有将输出电阻驱动到其CMOS电平的能力，以便最大限度地减小和吸收电流。

70. 发明公开

EP0547891A3 A precharging output driver circuit 失效
标题翻译：预置输出驱动电路
公开(公告)号：EP0547891A3
公开(公告)日：1993-12-08
申请号：EP92311513.3
申请日：1992-12-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Slemmer, William Carl
IPC分类号： H03K19/0175 , H03K19/003 , G11C7/00
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.

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