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61. 发明授权

EP0644594B1 Power supply wiring for semiconductor device 失效
标题翻译：的半导体装置的进料管线布置
公开(公告)号：EP0644594B1
公开(公告)日：1999-04-28
申请号：EP94114310.9
申请日：1994-09-12
申请人： NEC CORPORATION
发明人： Suzuki, Kazumasa, c/o NEC Corporation
IPC分类号： H01L23/50 , H01L27/02
CPC分类号： H01L27/0218 , H01L23/5286 , H01L2924/0002 , H01L2924/00

62. 发明公开

EP0836194A3 Semiconductor device 失效
标题翻译： Halbleiteranordnung
公开(公告)号：EP0836194A3
公开(公告)日：1999-03-10
申请号：EP97203535.6
申请日：1993-03-29
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Yamaguchi, Yasuo, Mitsubishi Denki K.K. LSI , Nishimura, Tadashi, Mitsubishi Denki K.K. LSI
IPC分类号： G11C5/14 , G11C11/407
CPC分类号： H03K19/0016 , G11C5/146 , G11C11/4074 , H01L27/0218 , H01L27/105
摘要： A semiconductor device including an NMOS transistor includes a first bias generating circuit 30 for generating a substrate bias VBB1 for making smaller the amount of leak current in an inactive state, a second bias generating circuit 31 for generating a substrate bias VBB2 for increasing drivability of supplying current in the active state of the NMOS transistor, and a bias selecting circuit 32 responsive to a control signal CNT for supplying the substrate bias VBB2 instead of the substrate bias VBB1 to the silicon substrate 1. By changing the potential of the substrate bias in the standby state and the active state, power consumption in the standby state can be reduced and the speed of operation in the active state can be improved.
摘要翻译：包括NMOS晶体管的半导体器件包括：第一偏压产生电路30，用于产生用于使无效状态下的漏电流量变小的衬底偏压VBB1;产生衬底偏置VBB2的第二偏压产生电路31，用于增加供电的驱动能力电流处于NMOS晶体管的激活状态;以及偏置选择电路32，其响应用于将衬底偏置VBB2而不是衬底偏压VBB1提供给硅衬底1的控制信号CNT。通过改变衬底偏置电位备用状态和活动状态，可以降低备用状态下的功耗，并且可以提高活动状态下的运行速度。

63. 发明授权

EP0690510B1 Low voltage SOI (silicon on insulator) logic circuit 失效
标题翻译： SOI（绝缘体上硅）逻辑电路用低电压
公开(公告)号：EP0690510B1
公开(公告)日：1998-05-06
申请号：EP95110014.8
申请日：1995-06-27
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： Douseki, Takakuni
IPC分类号： H01L27/12
CPC分类号： H01L27/12 , H01L27/0218

64. 发明公开

EP0810668A1 Silicon on insulator master slice semiconductor integrated circuit 失效
标题翻译： Kundenspezifische integrierte Halbleiterschaltung mit Silizium-auf-Isolatorstruktur
公开(公告)号：EP0810668A1
公开(公告)日：1997-12-03
申请号：EP97108647.5
申请日：1997-05-28
申请人： NEC CORPORATION
发明人： Kumagai, Kouichi
IPC分类号： H01L27/118 , H01L27/02
CPC分类号： H01L27/0218 , H01L27/11807
摘要： A master slice semiconductor IC has a SOI substrate and a plurality of basic cells arranged in a matrix on the SOI substrate. The basic cell includes a two-input NAND gate and a diode forward biased between one of power supply lines and the NAND gate. The diode has a P-N junction extending between the top surface of a semiconductor layer and the insulator layer underlying the semiconductor layer. The diode reduces the supply voltage by the forward drop voltage thereof to reduce power consumption in the NAND gate, and the SOI structure of the basic cell prevents reduction of integration density and operational speed.
摘要翻译：主分片半导体IC具有在SOI衬底上以矩阵形式布置的SOI衬底和多个基本单元。基本单元包括双输入NAND门和正向偏置在电源线和NAND门之一之间的二极管。二极管具有在半导体层的顶表面和半导体层下面的绝缘体层之间延伸的P-N结。二极管通过其正向下降电压来降低电源电压，以降低与非门的功耗，并且基本单元的SOI结构防止了集成密度和操作速度的降低。

65. 发明公开

EP0805557A2 Semiconductor integrated circuit device 失效
标题翻译： Vorrichtung mit integrierter Halbleiterschaltung
公开(公告)号：EP0805557A2
公开(公告)日：1997-11-05
申请号：EP97107187.3
申请日：1997-04-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kuroda, Tadahiro , Sakurai, Takayasu
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H01L27/0218 , H01L2224/05554 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/13091 , H01L2924/3011 , H01L2924/30111 , H03K19/00384 , H03K19/018507 , H01L2924/00 , H01L2224/45099
摘要： To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit (1) for generating a predetermined voltage fixed between a first supply voltage (GND) and a second supply voltage (V DD ); a driver circuit (5) for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit (1) and the first supply voltage (GND), and for driving a transfer path by the converted signal; a voltage divider circuit (9) for dividing an output voltage of the bias circuit; and a receiver circuit (10) for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.
摘要翻译：为了最小化功率消耗，所公开的半导体集成电路器件包括：用于产生固定在第一电源电压（GND）和第二电源电压（VDD）之间的预定电压的偏置电路（1）; 驱动电路（5），用于接收每个在第一和第二电源电压之间振动的反相输入信号和非反相输入信号，用于将接收的输入信号转换成在偏置电路（1）的输出电压之间振动的信号，和第一电源电压（GND），并且用于通过转换的信号驱动传输路径; 分压电路（9），用于分压偏置电路的输出电压; 以及接收器电路（10），用于通过使用分压器电路的输出作为参考电压来检测用于驱动传输路径的信号，并且用于将检测到的信号转换为在第一电源电压和第二电源之间振动的信号电压。

66. 发明授权

EP0539110B1 Integrated circuit having a boosted node 失效
标题翻译：一种集成电路，包括充电节点
公开(公告)号：EP0539110B1
公开(公告)日：1997-04-23
申请号：EP92309450.2
申请日：1992-10-16
申请人： AT&T Corp.
发明人： Lee, Hyun
IPC分类号： H01L27/02 , G11C8/00 , G11C11/408
CPC分类号： H01L27/0218

67. 发明公开

EP0644594A1 Power supply wiring for semiconductor device 失效
标题翻译： Speiseleitungen-Anordnung einer Halbleitervorrichtung。
公开(公告)号：EP0644594A1
公开(公告)日：1995-03-22
申请号：EP94114310.9
申请日：1994-09-12
申请人： NEC CORPORATION
发明人： Suzuki, Kazumasa, c/o NEC Corporation
IPC分类号： H01L23/50 , H01L27/02
CPC分类号： H01L27/0218 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed. The size of the capacitor is half in length as large as the width of the power supply wiring, and the width substantially equals the length of the power supply wiring, the parasitic resistance generated at the gate or inversion layer is suppressed small, and the gate capacitance approximately corresponding to the area of master power supply wiring is interposed between the power source and the ground. As a result, a large capacitance bypass capacitor can be formed between the power source and the ground, and a power supply wiring which is great in effect of eliminating power supply noise can be obtained.
摘要翻译：接地线2被设置成夹着电源线1.栅极氧化膜3和栅极4形成在电源线1的下方。邻近栅极氧化膜的端部形成n型区域8 为其设置地下潜力。在地线下方的剩余部分的大部分上形成p型区域9，使其与基板接触。由于栅极的电位等于电源的电位，所以在氧化膜的下方形成反型层，其中地电位通过n型区域产生。通过将栅极氧化膜夹在栅极和反转层之间，形成电容器。电容器的尺寸长度与电源布线的宽度一样大，并且宽度基本上等于电源布线的长度，在门或反转层处产生的寄生电阻被抑制得较小，并且栅极大致对应于主电源布线的面积的电容插入在电源和地之间。结果，可以在电源和地之间形成大的电容旁路电容器，并且可以获得有效消除电源噪声的电源布线。

68. 发明公开

EP0564204A2 Semiconductor device 失效
标题翻译： Halbleiteranordnung。
公开(公告)号：EP0564204A2
公开(公告)日：1993-10-06
申请号：EP93302415.0
申请日：1993-03-29
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Yamaguchi, Yasuo, c/o Mitsubishi Denki K.K. LSI , Nishimura, Tadashi, c/o Mitsubishi Denki K.K. LSI
IPC分类号： G11C5/14 , G11C11/407
CPC分类号： H03K19/0016 , G11C5/146 , G11C11/4074 , H01L27/0218 , H01L27/105
摘要： A semiconductor device including an NMOS transistor includes a first bias generating circuit 30 for generating a substrate bias VBB1 for making smaller the amount of leak current in an inactive state, a second bias generating circuit 31 for generating a substrate bias VBB2 for increasing drivability of supplying current in the active state of the NMOS transistor, and a bias selecting circuit 32 responsive to a control signal CNT for supplying the substrate bias VBB2 instead of the substrate bias VBB1 to the silicon substrate 1. By changing the potential of the substrate bias in the standby state and the active state, power consumption in the standby state can be reduced and the speed of operation in the active state can be improved.
摘要翻译：包括NMOS晶体管的半导体器件包括：第一偏压产生电路30，用于产生用于使无效状态下的漏电流量变小的衬底偏压VBB1;产生衬底偏置VBB2的第二偏压产生电路31，用于增加供电的驱动能力电流处于NMOS晶体管的激活状态;以及偏置选择电路32，其响应用于将衬底偏置VBB2而不是衬底偏压VBB1提供给硅衬底1的控制信号CNT。通过改变衬底偏置电位备用状态和活动状态，可以降低备用状态下的功耗，并且可以提高活动状态下的运行速度。

69. 发明授权

EP0305937B1 MOS i/o protection using switched body circuit design 失效
标题翻译：使用开关体电路设计的MOS I / O保护
公开(公告)号：EP0305937B1
公开(公告)日：1993-05-19
申请号：EP88114012.3
申请日：1988-08-27
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Miller, William E.
IPC分类号： H01L27/02
CPC分类号： H01L27/0251 , H01L27/0218 , H03K17/08104 , H03K19/00315

70. 发明公开

EP0287147A3 Monolithic integrated power circuit in semibridge configuration, particularly for piloting electric motors 失效
标题翻译：半导体配置中的单片集成电源电路，特别适用于电动马达
公开(公告)号：EP0287147A3
公开(公告)日：1992-07-15
申请号：EP88200565.5
申请日：1988-03-25
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Ferla, Giuseppe , Musumeci, Salvatore
IPC分类号： H01L27/082 , H01L27/088 , H01L27/02 , H02P7/00
CPC分类号： H01L27/0814 , H01L27/0218 , H01L27/0825 , H02P7/04
摘要： Two switches (1, 2) connected in series are formed in respective parallel zones of a silicon substrate (21) in such a manner as to form straight current flows in opposite directions between respective power terminals (3, 4) of opposite polarity formed on the same surface (27) of the substrate (21) and an intermediate terminal provided on the opposite surface (41) of the substrate (21).

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