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51. 发明公开

EP0006468A2 Parallel to series data converters 失效
标题翻译： Parallel-Serienumsetzung von Daten。
公开(公告)号：EP0006468A2
公开(公告)日：1980-01-09
申请号：EP79101695.9
申请日：1979-06-01
申请人： International Business Machines Corporation
发明人： Allen, Francis Kempton , Chin, Victor Huie
IPC分类号： G06F5/04 , H04L25/45
CPC分类号： H04L25/45 , H03M9/00
摘要： The converter comprises a data source (10) from which half-bytes of data are supplied in a parallel-by-bit, serial-by-half-byte manner to data registers (14, 16). The supply is controlled by control logic (18) so that register (14) is being filled while register (16) is being emptied and vice versa. Data from the registers (14, 16) are supplied to steering circuits (28, 30, 32, 34) which act as gating circuits. Circuits (28, 30) are gated by a first signal taken from counter (20) and circuits (32, 34) by a second signal taken from the counter. The first and second signals are in anti-phase and are operative so that in one quarter cycle bits (0, 1) are gated through circuits (28, 30); in the second quarter cycle bits (2, 3) are gated through circuits (32, 34); in the third quarter cycle bits (4, 5) are gated through circuits (28, 30); and in the fourth quarter cycle bits (6, 7) are gated through circuits (32, 34). The sample and interleave circuit (36) receives the signals gated through circuits (28, 30, 32, 34) and is operative, under the control of sample (A, B, C, D) timing signals, to sample and gate to a common output line, the outputs of the circuits (28, 30; 32, 34; 28, 30; 32, 34) during the four quarter cycles, two sampling being made serially every quarter cycle.
摘要翻译：该转换器包括数据源（10），半字节的数据以逐个字节的逐字节方式提供给数据寄存器（14,16）。供应由控制逻辑（18）控制，使得寄存器（14）正在被填充，而寄存器（16）被清空，反之亦然。来自寄存器（14,16）的数据被提供给用作选通电路的转向电路（28,30,32,34）。电路（28,30）由从计数器（20）和电路（32,34）取得的第一信号通过从计数器取出的第二信号来选通。第一和第二信号是反相的并且是可操作的，使得在四分之一周期中，位（0,1）通过电路（28,30）选通; 在第二季度周期中，位（2,3）通过电路（32,34）选通; 在第三季度周期中，位（4,5）通过电路（28,30）进行门控; 并且在第四个四分之一周期中，位（6,7）通过电路（32,34）选通。采样和交织电路（36）接收通过电路（28,30,32,34）门控的信号，并且在样本（A，B，C，D）定时信号的控制下操作，以采样和门控到公共输出线，在四个四分之一周期期间电路（28,30; 32,34; 28,30; 32,34）的输出，每四个周期进行两次采样。

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