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51. 发明公开

EP1575170A1 Highly configurable pll architecture for programmable logic device 有权转让
标题翻译： Hochkonfigurierbare Phasenregelschleifestrukturfüreinen programmierbaren logischen Baustein
公开(公告)号：EP1575170A1
公开(公告)日：2005-09-14
申请号：EP05251420.5
申请日：2005-03-09
申请人： ALTERA CORPORATION
发明人： Starr, Gregory W. , Chang, Wanli , Wei Lai, Kang , Smith, Mian Z. , Chang, Richard
IPC分类号： H03L7/18 , H03K5/13 , G06F1/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

52. 发明公开

EP1473619A1 Multiple clocks with superperiod 有权
标题翻译： Mehrere Takte mit Superperiode
公开(公告)号：EP1473619A1
公开(公告)日：2004-11-03
申请号：EP03101192.7
申请日：2003-04-30
申请人： Agilent Technologies, Inc.
发明人： Killig, Ralf
IPC分类号： G06F1/06
CPC分类号： G06F1/06
摘要： The invention provides an apparatus adapted for supplying a plurality of clock signals. The apparatus comprises a set of clock signal circuits for generating m clock signals of at least two different signal periods, with m being a natural number, and a superperiod signal-generating unit adapted for deriving, from a dedicated clock signal of said set of clock signals, a first superperiod signal. The signal period of said first superperiod signal is a common multiple of the clock signals' signal periods.
摘要翻译：本发明提供一种适于提供多个时钟信号的装置。该装置包括用于产生至少两个不同信号周期的m个时钟信号的一组时钟信号电路，其中m是自然数，并且超周期信号产生单元适于从所述时钟组的专用时钟信号中导出信号，第一超周期信号。所述第一超周期信号的信号周期是时钟信号的信号周期的公倍数。

53. 发明公开

EP1333578A3 Interleaved clock signal generator having serial delay and ring counter architecture 有权
标题翻译：用一系列-Verzögerungslemente和环形计数器具有架构交错时钟信号发生器
公开(公告)号：EP1333578A3
公开(公告)日：2004-03-10
申请号：EP02023233.6
申请日：2002-10-16
申请人： Agilent Technologies, Inc.
发明人： Neff, Robert, M., R.
IPC分类号： H03K5/15 , H03L7/081 , G06F1/06
CPC分类号： H03K5/15093 , H03K5/1504 , H03K5/1565 , H03L7/07 , H03L7/0812
摘要： The interleaved clock generator (100) generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type (102) for receiving the input clock signal and for generating M intermediate clock signals (Jl - JM) in response to the input clock signal. The interleaved clock generator of the first type includes either a multi-stage serial-delay circuit or a ring counter circuit. The interleaved clock generator additionally comprises M interleaved clock generators of a second type (104-1 to 104-M), each of which is each for receiving a respective one of the intermediate clock signals from the clock generator of the first type and for generating N/M of the N interleaved clock signals (K1 - KN) in response to the respective one of the intermediate clock signals. Each of the interleaved clock generators of the second type includes either a ring counter circuit or a multi-stage serial-delay circuit: a ring counter when the interleaved clock generator of the first type includes a multi-stage serial-delay circuit; a multi-stage serial-delay circuit when the interleaved clock generator of the first type includes a ring counter circuit.

54. 发明授权

EP0822478B1 Voltage converting circuit and multiphase clock generating circuit for driving the same 失效
标题翻译：电压转换电路和多相时钟产生器
公开(公告)号：EP0822478B1
公开(公告)日：2003-12-10
申请号：EP97118054.2
申请日：1993-09-02
申请人： NEC Electronics Corporation
发明人： Tamagawa, Akio
IPC分类号： G06F1/04 , H03K3/02 , H03K5/15 , G06F1/06
CPC分类号： H03K3/356026 , H02M3/07 , H02M2001/009 , H03K3/356121

55. 发明公开

EP1358535A1 HARDWARE INITIALIZATION WITH OR WITHOUT PROCESSOR INTERVENTION 审中-公开
标题翻译：有或无术硬件初始化处理
公开(公告)号：EP1358535A1
公开(公告)日：2003-11-05
申请号：EP02704401.5
申请日：2002-02-06
申请人： Emulex Corporation
发明人： SU, Sam , HASHEMI, Hossein , XUE, Qing
IPC分类号： G06F1/04 , G06F1/06 , G06F9/00 , G06F15/177
CPC分类号： G06F9/4403 , G06F1/24
摘要： In an embodiment, an initialization extension device (102) may provide an extended initialization period to enable a processor (104) to configure a device (106), for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device (106) may include a number of control registers (108) that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer (204) to countdown a timer extended initialization period. During the timer extended initialization period, the processor (104) may write an extension control signal, e.g., an extension bit (206), to a register. An initialization extension unit (102) may maintain the device (106) in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor (104) may configure the control registers (108) for one or more operations the device (106) may perform when it enters the operating mode.

56. 发明授权

EP0903650B1 Timer device comprising a timer counter, a register and a coincidence detecting circuit, and method for controlling an output terminal using such timer device 有权
标题翻译：间隔定时器与时间计数器，寄存器和一致检测电路和方法，用于控制使用这样的时间间隔定时器的输出电路
公开(公告)号：EP0903650B1
公开(公告)日：2002-04-10
申请号：EP98117738.9
申请日：1998-09-18
申请人： NEC CORPORATION
发明人： Oba, Kaori NEC Corporation
IPC分类号： G04F1/00 , G06F1/06
CPC分类号： G04F1/005 , G06F1/06

57. 发明公开

EP1105881A4 TECHNIQUES FOR ANALOG AND MULTILEVEL STORAGE USING INTEGRATED CIRCUIT TECHNOLOGY 审中-公开
标题翻译：技术为模拟和更大的存储LEVEL采用集成电路
公开(公告)号：EP1105881A4
公开(公告)日：2002-01-23
申请号：EP99930821
申请日：1999-06-29
申请人： SANDISK CORP
发明人： HAEBERLI ANDREAS M , WONG SAU C , SO HOCK C , WANG CHENG-YUAN MICHAEL , WONG LEON SEA JIUNN , WERNER CARL W
IPC分类号： G11C16/02 , G06F1/06 , G06F1/12 , G11C5/14 , G11C11/56 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/00 , G11C27/02 , G11C16/04
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Information is provided in analog (402) or digital (DI) form and is stored in the memory cells (412) of an integrated circuit (400). The memory cells of the integrated circuit are nonvolatile memory cells capable of analog or multilevel storage. The integrated circuit samples (230) the analog information and stores the samples in the memory cells (250) in an analog form. Typically, one cell holds one sample of the analog information. The sampling rate (625) is user-selectable, and an indication of the user's selection of the sampling stored within (661) the integrated circuit. Circuitry on the integrated circuit including charge pumps (3610, 3615, 3620) are adjusted (3423) to operate more effectively or efficiently depending on the supply voltage level (Vext). Level shifter circuitry (1810, 1815, 2430) on the integrated circuit is programmably adjustable. An internal signal path of the integrated circuit can be fully differential.

58. 发明公开

EP0903650A1 Timer device having timer counter 有权
标题翻译： Zeitintervallgeber mitZeitzähler
公开(公告)号：EP0903650A1
公开(公告)日：1999-03-24
申请号：EP98117738.9
申请日：1998-09-18
申请人： NEC CORPORATION
发明人： Oba, Kaori NEC Corporation
IPC分类号： G04F1/00 , G06F1/06
CPC分类号： G04F1/005 , G06F1/06
摘要： A coincidence signal is output when coincidence of a timer counter with the set value of a comparison register is detected by a coincidence detecting circuit and the coincidence signal is input to the external CPU as an interruption signal to execute a CPU to start an interruption routine. In the interruption routine, a reverse enable flag is set, a flag indicating permission to reverse an output signal when the value of a key counter is larger than the value of a buzzer counter and a reverse enable flag is set, a flag indicating prohibition of reversing the output signal when the value of the key counter is smaller than that of the buzzer counter.
摘要翻译：当一个定时器计数器与比较寄存器的设定值一致时，一致信号被一致检测电路检测到并且一致信号被输入到外部CPU作为中断信号，以执行CPU开始中断程序。在中断例程中，设置反向使能标志，当设置密钥计数器的值大于蜂鸣器计数器的值和反向使能标志时，指示允许反转输出信号的标志，指示禁止当键计数器的值小于蜂鸣器计数器的值时，反转输出信号。

59. 发明公开

EP0603996A3 Clock control apparatus 失效
标题翻译：时钟控制装置
公开(公告)号：EP0603996A3
公开(公告)日：1998-01-28
申请号：EP93307162.3
申请日：1993-09-10
申请人： FUJITSU LIMITED
发明人： Komatsuda, Hiroshi, c/o Fujitsu Limited
IPC分类号： G06F1/06
CPC分类号： G06F1/04
摘要： A clock control apparatus having a basic period clock and a plurality of clocks with different phases from the basic period clock by t/N period, is used with an information processing unit. The apparatus comprising a clock signal generating portion for generating pulses of the basic period clock, a cycle counter for counting the number of pulses of the basic period clock received from the clock signal generating portion when a start command is received and for outputting a cycle counter clock stop signal when the number of pulses becomes a predetermined count value, a control portion for outputting a basic enable period signal for controlling the basic period clock and a delay enable period signal for controlling the t/N period clocks by a flag and the cycle counter clock stop signal, the flag being assignable before the start command is received, a basic period clock enabling portion for receiving pulses of the basic period clock and for outputting the pulses of the basic period clock for a period designated by the basic enable period signal, and a t/N delay period clock enabling portion for generating pulses of the t/N period clock and for outputting the pulses for a period designated by the delay enable period signal.

60. 发明授权

EP0359177B1 Clock signal supplying device 失效
标题翻译：一种用于时钟信号供给
公开(公告)号：EP0359177B1
公开(公告)日：1996-06-05
申请号：EP89116782.7
申请日：1989-09-11
申请人： HITACHI, LTD.
发明人： Masuda, Noboru , Itoh, Hiroyuki , Fujita, Bunichi , Kawashima, Seiichi , Ishii, Shuichi
IPC分类号： G06F1/04 , G06F1/10 , G06F1/06 , G06F11/14
CPC分类号： G06F1/06 , G06F1/10

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