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51. 发明公开

EP1302978A3 Method of making a self-aligned ferroelectric memory transistor 审中-公开
标题翻译：一种制造自对准的存储器晶体管ferrroelektrischen的方法
公开(公告)号：EP1302978A3
公开(公告)日：2008-01-09
申请号：EP02023155.1
申请日：2002-10-15
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Li, Tingkai , Zhang, Fengyan
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/51 , H01L21/28291 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L29/516
摘要： A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.

52. 发明授权

EP1035589B1 Iridium composite barrier structure and method for same 有权
标题翻译：铱复合阻挡结构和它们的制备方法
公开(公告)号：EP1035589B1
公开(公告)日：2007-05-02
申请号：EP00301790.2
申请日：2000-03-06
申请人： SHARP KABUSHIKI KAISHA , Sharp Laboratories of America, Inc.
发明人： Zhang, Fengyan , Maa, Jer-Shen , Hsu, Sheng Teng
IPC分类号： H01L29/45 , H01L21/28
CPC分类号： H01L28/75 , H01L21/28291 , H01L28/55 , H01L29/516

53. 发明公开

EP1670045A3 Gate of a memory transistor with a ferroelectric layer and method of manufacturing the same 审中-公开
标题翻译：具有铁电体层和制造方法的存储器晶体管的栅极
公开(公告)号：EP1670045A3
公开(公告)日：2006-10-04
申请号：EP05026719.4
申请日：2005-12-07
申请人： SEIKO EPSON CORPORATION
发明人： Kijima, Takeshi , Hamada, Yasuaki , Higuchi, Takamitsu
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/51
CPC分类号： H01L29/6684 , H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A transistor type ferroelectric memory includes a group-IV semiconductor layer (10), an oxide semiconductor layer (20) formed over the group-IV semiconductor layer, a ferroelectric layer (30) formed over the oxide semiconductor layer, a gate electrode (40) formed over the ferroelectric layer, and a source region (12) and a drain region (14) formed in the group-IV semiconductor layer.
The group-IV semiconductor layer (10) and the oxide semiconductor layer (20) form a pn junction with a depletion layer at the interface of both layers. By controlling the fixed changes individual in the oxide semiconductor layer (20), the current flow between source (12) and drain (14) can be switched on or off.

54. 发明公开

EP1670045A2 Gate of a memory transistor with a ferroelectric layer and method of manufacturing the same 审中-公开
标题翻译：具有铁电体层和制造方法的存储器晶体管的栅极
公开(公告)号：EP1670045A2
公开(公告)日：2006-06-14
申请号：EP05026719.4
申请日：2005-12-07
申请人： SEIKO EPSON CORPORATION
发明人： Kijima, Takeshi , Hamada, Yasuaki , Higuchi, Takamitsu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78 , G11C11/34
CPC分类号： H01L29/6684 , H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A transistor type ferroelectric memory includes a group-IV semiconductor layer (10), an oxide semiconductor layer (20) formed over the group-IV semiconductor layer, a ferroelectric layer (30) formed over the oxide semiconductor layer, a gate electrode (40) formed over the ferroelectric layer, and a source region (12) and a drain region (14) formed in the group-IV semiconductor layer.
The group-IV semiconductor layer (10) and the oxide semiconductor layer (20) form a pn junction with a depletion layer at the interface of both layers. By controlling the fixed changes individual in the oxide semiconductor layer (20), the current flow between source (12) and drain (14) can be switched on or off.
摘要翻译：一种晶体管型铁电体存储器包含形成IV族半导体层上的氧化物半导体层上的IV族半导体层（10）（20），形成氧化物半导体层，栅电极上的铁电体层（30）（40 ）形成在所述强电介质层，和源极区（12）和IV族半导体层中形成的漏区（14）。 IV族半导体层（10）和氧化物半导体层（20）形成具有两个层的界面的耗尽层形成pn结。通过控制单独的氧化物半导体层（20）在固定的变化，源极（12）和漏极（14）之间的电流流动可以接通或关断。

55. 发明公开

EP1246254A3 MFOS memory transistor and method of fabricating same 有权
标题翻译： MFOS-Speicher-Transistor undDiebezüglichesHerstellungsverfahren
公开(公告)号：EP1246254A3
公开(公告)日：2004-10-20
申请号：EP02007061.1
申请日：2002-03-27
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Zhang, Fengyan , Li, Tingkai
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/516 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
摘要翻译：提供了具有铁电栅极和钝化侧壁的铁电晶体管栅极结构。钝化侧壁用作绝缘体以减少或消除氧或氢扩散到铁电栅极中。还提供了形成铁电栅极结构的方法。该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积钝化绝缘体材料，使用各向异性等离子体蚀刻蚀刻钝化绝缘体材料以形成钝化侧壁，沉积铁电材料，使用CMP抛光铁电材料;以及形成覆盖铁电材料的顶部电极。

56. 发明公开

EP1382060A1 SINGLE TRANSISTOR RARE EARTH MANGANITE fERROELECTRIC NONVOLATILE MEMORY CELL 审中-公开
标题翻译： FERRO电动挥发性不稀土锰单晶体管轮辐CELL
公开(公告)号：EP1382060A1
公开(公告)日：2004-01-21
申请号：EP02746319.9
申请日：2001-08-24
申请人： Cova Technologies Incorporated
发明人： GNADINGER, Fred P.
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L27/105 , H01L27/11509 , H01L28/56 , H01L29/516 , H01L29/78391
摘要： A memory device is formed of the one transistor cell type. Such a device has a substrate, a ferroelectric layer which is a film of rare earth manganite, and an interfacial oxide layer being positioned between the substrate and the ferroelectric layer. The invention includes such a device and methods of making the same.

57. 发明公开

EP1369926A2 Ferroelectric memory transistor and method for forming the same 审中-公开
标题翻译： Ferroelektrischer Speichertransistor和dessen Herstellungsverfahren
公开(公告)号：EP1369926A2
公开(公告)日：2003-12-10
申请号：EP03253199.8
申请日：2003-05-22
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Zhang, Fengyan , Li, Tingkai
IPC分类号： H01L29/423 , H01L29/78 , H01L21/8246
CPC分类号： G11C11/22 , H01L21/28291 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/11502 , H01L29/78391
摘要： An object of the present invention is to provide a non-volatile ferroelectric memory device, which eliminates leakage-related transistor memory retention degradation. A ferroelectric memory transistor according to the present invention comprises: a substrate having a source region (54), a gate region (58), and a drain region (56); a gate stack (60) located on the gate region, including: a high-k insulator element (62), including a first high-k cup (62L) and a second high-k cup (62U); a ferroelectric element (64), wherein said ferroelectric element is encapsulated within said high-k insulator element (62); and a top electrode (66) located on a top portion of said high-k insulator element; a passivation oxide layer (68) located over the substrate and gate stack; and metalizations (70,74,72) to form respective contacts to the source region, the drain region and the gate stack.
摘要翻译：本发明的目的是提供一种消除漏电相关晶体管存储器保持性降低的非挥发性铁电存储器件。根据本发明的铁电存储晶体管包括：具有源极区（54），栅极区（58）和漏极区（56）的衬底; 位于所述栅极区域上的栅叠层（60）包括：高k绝缘体元件（62），包括第一高k杯（62L）和第二高k杯（62U）; 铁电元件（64），其中所述铁电元件被封装在所述高k绝缘体元件（62）内; 以及位于所述高k绝缘体元件的顶部上的顶部电极（66）钝化氧化物层（68），其位于所述衬底和栅极堆叠之上; 和金属化（70,74,72）以形成到源极区域，漏极区域和栅极叠层的相应触点。

58. 发明公开

EP1345259A2 Polycrystalline memory structure, method for forming same structure, and semiconductor memory device using same structure 审中-公开
标题翻译：使用的这种结构的多晶存储器结构，其制造方法及半导体存储器件
公开(公告)号：EP1345259A2
公开(公告)日：2003-09-17
申请号：EP03251457.2
申请日：2003-03-11
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Li, Tingkai , Zhuang, Wei-Wei
IPC分类号： H01L21/02 , G11C11/00 , H01L21/28
CPC分类号： H01L28/56 , G11C13/0007 , G11C2213/31 , H01L21/28291 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： The invention provides a polycrystalline memory structure comprising: a polycrystalline memory layer (18) overlying a substrate (14) and having crystal grain boundaries forming gaps (20) between adjacent crystallites; and an insulating material (24) at least partially within the gaps.
摘要翻译：本发明提供的多晶存储器结构，包括：存储器的多晶层（18）覆盖衬底（14）和具有在相邻的晶体吸住之间的间隙（20）的晶界; 和部分内的间隙的绝缘至少材料（24）的。

59. 发明公开

EP1224699A1 RAPID RAMPING ANNEAL METHOD FOR FABRICATING SUPERLATTICE MATERIALS 审中-公开
标题翻译：用于生产材料网格结构BYSCHNELLRAMPGLÜHEN
公开(公告)号：EP1224699A1
公开(公告)日：2002-07-24
申请号：EP01908955.6
申请日：2001-02-07
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： UCHIYAMA, Kiyoshi , ARITA, Koji , SOLAYAPPAN, Narayan , PAZ DE ARAUJO, Carlos, A.
IPC分类号： H01L27/11 , C30B29/68
CPC分类号： H01L21/28291 , C30B7/00 , C30B7/005 , C30B29/68
摘要： A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal ("RRA") technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.

60. 发明公开

EP1035588A3 Iridium conductive electrode/barrier structure and method for same 有权
标题翻译： Leitende Elektrode aus Iridium und Barrierestruktur und Verfahren zur Herstellung
公开(公告)号：EP1035588A3
公开(公告)日：2002-03-20
申请号：EP00301789.4
申请日：2000-03-06
申请人： SHARP KABUSHIKI KAISHA , Sharp Laboratories of America, Inc.
发明人： Zhang, Fengyan , Maa, Jer-Shen , Hsu, Sheng Teng
IPC分类号： H01L29/45 , H01L21/28
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65
摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.
摘要翻译：已经提供了具有高温稳定性的用作铁电电容器电极的导电屏障。该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。已经发现将硅衬底与Ir膜分隔开，其间隔相邻的钽（Ta）膜在抑制层之间的扩散方面非常有效。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。这种Ir / TaN结构保护了硅界面，使得粘附，电导，小丘和剥离问题最小化。使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。还提供了形成多层Ir导电结构和Ir铁电电极的方法。

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