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41. 发明授权

EP2504962B1 MIMO MINIMUM MEAN SQUARE ERROR RECEIVER USING QR DECOMPOSITION AND SYSTOLIC ARRAYS 有权
标题翻译： MIMO最小AVERAGING方误差接收机QR切割和脉动阵列
公开(公告)号：EP2504962B1
公开(公告)日：2016-05-18
申请号：EP10735159.5
申请日：2010-07-20
申请人： Xilinx, Inc.
发明人： MAZAHREH, Raied, N. , TARN, Hai-Jo , RAO, Raghavendar, M.
IPC分类号： H04L25/02 , G06F15/80 , G06F17/16
CPC分类号： G06F17/16 , G06F7/78 , G06F15/8046 , H04B7/0413 , H04B7/0854 , H04L25/0244

42. 发明公开

EP1504533A2 PROCESSING METHOD AND APPARATUS FOR IMPLEMENTING SYSTOLIC ARRAYS 审中-公开
标题翻译：履行收缩GATE处理器的处理方法和设备
公开(公告)号：EP1504533A2
公开(公告)日：2005-02-09
申请号：EP03708428.2
申请日：2003-04-01
申请人： Koninklijke Philips Electronics N.V.
发明人： DE OLIVEIRA KASTRUP PEREIRA, Bernardo
IPC分类号： H04B1/00
CPC分类号： G06F15/8046
摘要： The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a predetermined sequence, and are supplied to a processing means (FU) for processing said input data based on control signals generated from instruction data, 5 wherein the depth of the register means (DCF) is controlled in accordance with the instruction data. Thereby, systolic arrays can be mapped onto a programmable processor, e.g. a VLIW processor, without the need for explicitly issuing operations to implement the register moves that constitute the delay lines of the array.

43. 发明公开

EP1278128A3 Systolic array device 审中-公开
标题翻译：收缩期Matrixvorrichtung
公开(公告)号：EP1278128A3
公开(公告)日：2004-09-08
申请号：EP02015672.5
申请日：2002-07-17
申请人： NTT DoCoMo, Inc.
发明人： Asai, Takahiro, NTT DoCoMo, Inc. Intel.Prop.Dept. , NTT DoCoMo, Inc. Int.Pty.Dep., Matsumoto Tdadashi , Tomisato, Shigeru, NTT DoCoMo, Inc.Intel.Prop
IPC分类号： G06F15/80 , H03H21/00
CPC分类号： G06F15/8046
摘要： When a plurality of reference signal series are handled with the same input signal series during processing of an RLS algorithm based on QR decomposition, an object is to handle the plurality of reference signal series simultaneously. When performing processing of a sequential least-squares algorithm based on QR decomposition, to a configuration comprising a plurality of boundary cells (empty circles) which calculate appropriate rotation parameters for transformations based on Givens rotation, a plurality of internal cells (squares) which cause rotation of elements of a received data vector using the calculated values of the boundary cells (empty circles), and a final cell (double circles) which derives the a posteriori estimated error from the calculated values of the boundary cells (empty circles) and internal cells (squares), additional internal cells (squares) within 21 are connected so as to receive signals output from each of the internal cells (squares) arranged in the end cell column to which the signal series is input, and to the final cell (double circles) is connected an additional final cell (double circles) within 21, so as to receive the calculated values from the boundary cells (empty circles) and the calculated values from the additional internal cells (square) input to the additional final cell (double circles).

44. 发明授权

EP0543860B1 DIGITAL PROCESSOR FOR SIMULATING OPERATION OF A PARALLEL PROCESSING ARRAY 失效转让
标题翻译：数字处理器进行操作的计算机并口模拟屏的
公开(公告)号：EP0543860B1
公开(公告)日：1996-03-06
申请号：EP91914359.4
申请日：1991-08-15
申请人： Secretary of State for Defence in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland
发明人： JOHNSON, Martin , JONES, Robin , BROOMHEAD, David Sidney
IPC分类号： G06F15/80
CPC分类号： G06F15/8046
摘要： A digital processor for simulating operation of a parallel processing array incorporates digital processing units (P1 to P8) communicating data to one another via addresses in memories (M0 to M8) and registers (R11 to R41). Each processing unit (e.g. P1) is programmed to input data and execute a computation involving updating of a stored coefficient followed by data output. Each computation involves use of a respective set of data addresses for data input and output, and each processing unit (e.g. P1) is programmed with a list of such sets employed in succession by that unit. On reaching the end of its list, the processing unit (e.g. P1) repeats it. Each address set is associated with a conceptual internal cell location in the simulated array (10), and each list is associated with a respective sub-array of the simulated array (10). Data is input cyclically to the processor (40) via input/output ports (I/O5 to I/O8) of some of the processing units (P5 to P8). Each processing unit (e.g. P1) executes its list of address sets within a cycle at a rate of one address set per subcycle. At the end of its list, each of the processing units (P1 to P8) has executed the functions associated with a conceptual respective sub-array of simulated cells (12), and the processor (40) as a whole has simulated operation of one cycle of a systolic array (10). Repeating the address set lists with further processor input provides successive simulated array cycles.

45. 发明授权

EP0220474B1 Wellenfrontfeldrechner 失效
标题翻译：波前阵列计算机
公开(公告)号：EP0220474B1
公开(公告)日：1993-06-16
申请号：EP86112898.1
申请日：1986-09-18
申请人： Lang, Hans-Werner
发明人： Lang, Hans-Werner
IPC分类号： G06F15/16
CPC分类号： G06F15/8046

46. 发明授权

EP0246911B1 Improvements in or relating to multistage electrical signal processing apparatus 失效
标题翻译：改进或涉及多电子信号处理设备
公开(公告)号：EP0246911B1
公开(公告)日：1992-11-11
申请号：EP87304561.1
申请日：1987-05-21
申请人： INMOS LIMITED
发明人： Yassaie, Mohamad Hossein , King-Smith, Anthony David , Dyson, Clive Malcolm
IPC分类号： G06F15/76
CPC分类号： G06F15/8046

47. 发明授权

EP0186958B1 Digital data processor for matrix-vector multiplication 有权转让
标题翻译：用于矩阵矢量多路复用的数字数据处理器
公开(公告)号：EP0186958B1
公开(公告)日：1992-06-10
申请号：EP85308310.3
申请日：1985-11-14
申请人： NATIONAL RESEARCH DEVELOPMENT CORPORATION
发明人： Ward, Jeremy
IPC分类号： G06F7/52 , G06F15/76 , G06F15/332
CPC分类号： G06F17/16 , G06F7/525 , G06F15/8046 , G06F17/15 , G06F2207/3884

48. 发明公开

EP0471723A1 DIGITAL PROCESSOR FOR TWO'S COMPLEMENT COMPUTATIONS 有权转让
标题翻译：数字处理器的两个补充
公开(公告)号：EP0471723A1
公开(公告)日：1992-02-26
申请号：EP90907199.0
申请日：1990-05-02
申请人： THE SECRETARY OF STATE FOR DEFENCE IN HER BRITANNIC MAJESTY'S GOVERMENT OF THE UNITED KINGDOM OF GREAT BRITAIN AND
发明人： McWHIRTER, John, Graham , WARD, Jeremy, Stuart , KNOWLES, Simon, Christian
IPC分类号： G06F7 , G06F15 , G06F17
CPC分类号： G06F15/8046 , G06F7/5443 , G06F17/16 , G06F2207/3892
摘要： Un processeur numérique (10) pour calculs de compléments à deux incorpore un réseau (12*) de cellules multiplicateurs (12), chacune desdites cellules étant dotée d'une fonction logique d'additionneur complet à porte d'un bit. Ledit réseau (12*) comprend des connexions entre voisins immédiats (16, 18, 20) munies de bascules déclenchées par une horloge (42, 44, 50) pour la propagation de bits. A chaque rythme, les cellules (12) reçoivent des données, des bits de retenue et des bits de somme cumulative. Chaque cellule (12) ajoute les bits de retenue et les bits de somme cumulative au produit du bit de données et une mantisse associé à la cellule pertinente (12). Les bits de données passent par les rangées du réseau et les bits de somme s'accumulent en cascade dans les colonnes dudit réseau. Les bits de retenue sont remis en circuit. Chaque mantisse est exprimée sous forme de bit de signe et au moins un bit de grandeur qui consiste en ou comprend un bit de niveau. Chaque cellule (12) comprend des moyens de déclenchement multiplicateur (58, 62) sensible aux bits de signe et de niveau, qui reportent des moyens de réaction (60, 66) sensible à un indicateur du bit de données le moins significatif de manière à remplacer le bit de réaction par un bit de signe. Chaque mantisse peut comprendre un bit de grandeur exprimé sous forme de bit de décalage, dont on se sert pour sélectionner la signification de bit de données multiplicande, les moyens de déclenchement (58, 62) étant sensibles au bits indicateurs de manière à éliminer les produits de bits d'extension de signe non voulus. Le processeur (10 ou 200) peut comprendre également des moyens d'accumulation (14 ou 214) incorporant des portes (90, 98 ou 292, 336) sensibles aux bits indicateurs et aménagées de manière à éliminer des bits d'extension de signe à résultats non voulus.
摘要翻译：用于补充计算的数字处理器（10）包括乘法器单元（12）的阵列（12 *），所述单元中的每一个都具有完整的按位加法器逻辑功能。所述网络（12 *）包括设置有由用于比特传播的时钟（42,44,50）触发的锁存器的直接邻居（16,18,20）之间的连接。在每个速率下，单元（12）接收数据，保持比特和累加和比特。每个单元（12）将进位比特和累加和比特加到数据比特和与相关单元（12）相关的尾数的乘积上。数据位通过网络的各行并且和位在所述网络的列中级联累积。保持位重新打开。每个尾数表示为一个符号位和至少一个包含或包含一个级别位的幅度位。每个单元（12）包括符号和级别符号敏感的乘法器触发装置（58,62），其响应于最低有效数据位的指示符而报告响应装置（60,66），以便用符号位替换反应位。每个尾数可以包括表示为偏移位的幅度的一个位，该位用于选择被乘数据位的含义，触发装置（58,62）响应指示位以便消除乘积。不需要的符号扩展位。处理器（10或200）还可以包括结合指示位敏感门（90,98或292,336）的存储装置（14或214），该指示位敏感门设置成消除符号扩展位到不想要的结果。

49. 发明公开

EP0169010A3 Systolic array for solving cyclic loop dependent algorithms 失效
标题翻译：用于解决循环循环算法的SYSTOLIC ARRAY ARRAY
公开(公告)号：EP0169010A3
公开(公告)日：1988-01-27
申请号：EP85304753
申请日：1985-07-03
申请人： FORD AEROSPACE & COMMUNICATIONS CORPORATION
发明人： Parvin, Bahram Alizadeh
IPC分类号： G06F15/06
CPC分类号： G06F15/8046
摘要： A systolic array (1) for reducing the time required to solve an algorithm having cyclic loop dependency, i.e., nested loops in which values calculated by inner loops depend upon indices of said inner loops and upon indices of outer loops. The array (1) comprises a chain of several identical sequentially connected cells. In the preferred embodiment, each cell, except for first and last cells in the chain, is connected to its two adjacent cells only. Multiprocessing is employed: at certain times during the algorithm solving, more than one cell is simultaneously activated to perform portions of the solving, so that the total time required to solve the algorithms is shortened to be a linear function of n and m. The algorithm can represent measurement of the distance between two symbolic strings, or other problems in artificial intelligence or logic. The algorithm is broken up into nm subalgorithms D(i,j); at each processing step, those subalgorithms D(i,j) are solved for which sufficient informations exists for their solution. In the illustrated example, this condition is represented by diagonally time-slicing a two-dimensional matrix having as elements each of the subalgorithms D(i,j).

50. 发明公开

EP0144123A3 Digital data processor for multiplying data elements by coefficients 失效
标题翻译：数字数据处理器，用于通过系数数据元素进行数据处理
公开(公告)号：EP0144123A3
公开(公告)日：1986-03-19
申请号：EP84306215
申请日：1984-09-10
申请人： NATIONAL RESEARCH DEVELOPMENT CORPORATION
发明人： McCanny, John Vincent Dept. of Elect. & Electronic , McWhirter, John Graham , Wood, Kenneth William
IPC分类号： G06F15/347
CPC分类号： G06F15/8046 , G06F17/15
摘要： A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array (70) of cells (71) consisting of nearest neighbour connected gated full adders. The cells (71) multiply data bits received from laterally adjacent cells (70) and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell (71) below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array (70). An adder tree (110) accumulates non-simultaneously computed contributions to individual output terms. The tree (110) incorporates a delay (122) and switches (120, 121) arranged to implement or bypass the delay (122) according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

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