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    • 45. 发明公开
    • Spring structure and method
    • Federstruktur和Methode
    • EP1176635A3
    • 2003-04-16
    • EP01305899.5
    • 2001-07-09
    • Xerox Corporation
    • Fork, David K.Ho, Jackson H.Lau, Rachel King-HaLu, Jeng Ping
    • H01L21/48H01L23/48B81B3/00G01R1/067G01R1/073
    • G01R1/06716B81B2203/0118B81C1/00484B81C2201/0136B81C2203/058G01R1/06727G01R1/07342G01R3/00H01L23/49811H01L2924/0002H01R4/48H01R12/57H05K3/4092Y10T29/4913Y10T29/49135Y10T29/4914H01L2924/00
    • Efficient methods for lithographically fabricating spring structures onto a substrate (301) containing contact pads or metal vias (305) by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material (310) is self-aligned to the spring metal finger (320) using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad or metal via, and also to further anchor the spring metal finger to the substrate.
    • 通过使用单个掩模通过形成弹簧金属和释放材料层,将含有接触垫或金属过孔的弹性结构光刻制造到衬底上的高效方法。 具体地,使用光致抗蚀剂掩模或电镀金属图案,或使用剥离处理技术,释放材料垫与弹簧金属指自对准。 然后使用释放掩模来释放弹簧金属指,同时保持将弹簧金属指的锚定部分固定到基底的释放材料的一部分。 当释放材料是导电的(例如钛)时,该释放材料部分直接位于接触垫或金属通孔上方,并且用作在完成的弹簧结构中的弹簧金属指的导管。 当释放材料不导电时,形成金属带以将弹簧金属指连接到接触垫或金属通孔,并且还将弹簧金属指状物进一步锚定到基底。
    • 49. 发明公开
    • Making and testing an integrated circuit using high density probe points
    • Fabrikation und Testen von integrierten Schaltungen mit Testpunkten hoher Dichte
    • EP0845680A1
    • 1998-06-03
    • EP97122519.8
    • 1991-02-14
    • LEEDY, Glenn J.
    • LEEDY, Glenn J.
    • G01R31/316
    • G11C29/006G01R1/06716G01R1/07307G01R1/07314G01R1/0735G01R31/2831G01R31/2863G01R31/287G01R31/2886G01R31/318505G01R31/318511G01R31/31905G01R31/31912G03F7/70466G03F7/70658H01L22/22H01L2924/15192H01L2924/3011Y10T29/4913Y10T29/49155Y10T29/49764
    • Each transistor or logic unit on an integrated wafer (1) is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer syste. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than wich conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by specially fabricated flexible tester surface (10) made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points (15-1, 15-2) on one side of the test surface (10). The probe points (330) electrically contact the contacts (2-1, 2-2) on the wafer (1) under test by fluid pressure.
    • 在互连金属化之前测试集成晶片(1)上的每个晶体管或逻辑单元。 通过CAD软件,修改了晶体管或逻辑单元布局网表,以替代有缺陷的冗余无缺陷逻辑单元。 然后在CAD计算机系统的控制下布线和图案化互连金属化。 因此,晶片中的每个管芯具有其自己的互连方案,尽管每个管芯在功能上是等效的,并且产量远高于在完成的电路级别的常规测试。 单个晶体管或逻辑单元测试通过在几层柔性二氧化硅的一个实施例中制造的特殊制造的柔性测试仪表面(10)来实现,每个层包含通孔和导电迹线,导通数千个微观金属探针点(15-1, 15-2)在测试表面(10)的一侧。 探针点(330)通过流体压力与待测晶片(1)上的触点(2-1,2-2)电接触。