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41. 发明公开

EP1052691A3 Laser decapsulation apparatus and method 审中-公开
标题翻译： Laserentkapselungsapparat和Verfahren
公开(公告)号：EP1052691A3
公开(公告)日：2003-11-05
申请号：EP00108967.1
申请日：2000-04-27
申请人： Intersil Corporation
发明人： Lowry, Robert
IPC分类号： H01L21/56
CPC分类号： B23K26/0853 , B23K2201/40 , H01L21/56 , H01L22/20 , H01L2924/0002 , Y10S438/94 , H01L2924/00
摘要： A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust part 9 removes debris and fumes. The device 24 is positioned and scanned using an X,Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.
摘要翻译：解封装置100具有从装置24去除塑料密封剂的激光器8.密封腔室20。排气部分9去除碎屑和烟雾。装置24使用X，Y工作台2定位和扫描。铰接端4将装置相对于激光器8旋转到锐角。端点检测器10感测暴露的集成电路并移动或关闭激光 8.

42. 发明公开

EP1107552A3 Apparatus and method for testing subscriber loop interface circuits 审中-公开
标题翻译：装置和方法用于测试用户环路接口电路
公开(公告)号：EP1107552A3
公开(公告)日：2003-07-16
申请号：EP99124664.6
申请日：1999-12-10
申请人： Intersil Corporation
发明人： Ludeman, Christopher
IPC分类号： H04M3/22 , H04M19/00 , H04M3/00
CPC分类号： H04M3/005 , H04M3/30
摘要： A method and apparatus for internally testing portions of a subscriber loop interface circuit. Testing is conducted on a semiconductor circuit including the subscriber loop interface circuit. The portion of the subscriber loop interface circuit being tested may be the ring trip detector and/or the off-hook detect circuit. Testing of may be conducted without disabling the capability of the subscriber loop interface circuit to monitor the hook status of a subscriber.

43. 发明公开

EP0984657A3 Programmable subscriber loop interface circuit and method 审中-公开
标题翻译：可编程用户线接口电路及其方法
公开(公告)号：EP0984657A3
公开(公告)日：2002-11-27
申请号：EP99117186.9
申请日：1999-09-01
申请人： Intersil Corporation
发明人： Ludeman, Christopher
IPC分类号： H04Q11/04 , H04M19/00
CPC分类号： H04Q11/04 , H04Q2213/13003 , H04Q2213/13082 , H04Q2213/1319 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/13381
摘要： A subscriber loop interface circuit (32) and method for externally programming the on-hook, off-hook, and transition states of the subscriber loop interface circuit (40). The circuit having an off-hook overhead sufficient for long loop applications and having a continuous loop current to loop voltage relationship. The circuit may have plural means for generating reference currents for comparison with loop currents.

44. 发明公开

EP1047135A3 Fast turn-off power semiconductor devices 审中-公开
标题翻译：具有快速关断功率半导体器件
公开(公告)号：EP1047135A3
公开(公告)日：2002-04-17
申请号：EP00401111.0
申请日：2000-04-20
申请人： Intersil Corporation
发明人： Hao, Jifa
IPC分类号： H01L29/86 , H01L29/739 , H01L29/16
CPC分类号： H01L29/04 , H01L29/861 , H01L29/868
摘要： A semiconductor switch is provided with fast turn-off characteristics by the mechanism of rapid recombination of minority carriers within a charge injecting region of the device. The region itself, or a portion of each of a plurality of parallelconnected such regions, comprises a body of highly doped polycrystalline silicon comprising tiny mono-crystalline grains of silicon joined at boundaries between the grains. The grain boundaries provide deep level energy traps for the capture and rapid annihilation, by recombination, of minority carriers within the polycrystalline body. An electrode is ohmically contacted with the one or each polycrystalline silicon body for efficient injection of majority carriers into the body.

45. 发明公开

EP1065711A3 Method of manufacturing a plated electronic termination 审中-公开
标题翻译： Verfahren zur Herstellung eines plattierten elektronischen Leiteranschluss
公开(公告)号：EP1065711A3
公开(公告)日：2001-11-07
申请号：EP00109592.6
申请日：2000-05-05
申请人： Intersil Corporation
发明人： Kwoka, Mark , Linn, Jack
IPC分类号： H01L21/48 , H01L23/495
CPC分类号： H01L23/49582 , H01L21/4842 , H01L24/48 , H01L24/97 , H01L2224/48247 , H01L2224/85464 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , Y10T29/49121 , Y10T29/49204 , Y10T29/49211 , Y10T29/49218 , Y10T29/49224 , H01L2224/45099 , H01L2924/00
摘要： A method of making a lead finish incorporating mechanically flattening the plated coating of metal leads. This may be accomplished by mechanical means such as rolling, stamping, peening, coining, forging.
摘要翻译：一种制造导线整理的方法，其包括机械地平坦化金属引线的镀覆涂层。这可以通过诸如轧制，冲压，喷丸，压印，锻造的机械手段来实现。

46. 发明公开

EP1128566A2 Biased-corrected rake receiver for direct sequence spread spectrum waveform 审中-公开
标题翻译：用于直接序列扩频波形的偏置纠正瑞克接收机
公开(公告)号：EP1128566A2
公开(公告)日：2001-08-29
申请号：EP01101976.7
申请日：2001-01-29
申请人： Intersil Corporation
发明人： Webster, Mark , Nelson, George , Halford, Steven
IPC分类号： H04B1/707
CPC分类号： H04B1/7115 , H04B1/7093
摘要： The performance of a RAKE receiver for indoor multipath WLAN applications on direct sequence spread spectrum signals having relatively short codeword lengths comprises a channel-matched filter and codeword correlator front end, plus a signal combiner to which the codeword correlation component is applied. The signal combiner is supplied with a bias-corrected input calculated by a distorted codeword signature (power) generator, which is operative to generate and store a set of N codeword power correction values. The signal combiner combines correction values into the codeword correlation for each potentially transmitted codeword S k . This serves to correct each correlation codeword metric by a de-biasing power component |S k | 2 for the unequal multipath-based distortions of the codeword energies. The output of the signal combiner is coupled to a peak detector, which selects a minimum distance-based 'de-biased' output as the transmitted codeword.
摘要翻译：用于室内多径WLAN应用的RAKE接收机对具有相对短的码字长度的直接序列扩频信号的性能包括信道匹配滤波器和码字相关器前端，以及加上码字相关分量的信号组合器。信号组合器被提供有由失真的码字签名（功率）生成器计算的偏差校正的输入，其可操作以生成并存储一组N个码字功率校正值。信号组合器将校正值组合为每个可能发送的码字Sk的码字相关。这用于通过针对码字能量的不相等的基于多径的失真的去偏置功率分量| Sk | 2来校正每个相关码字度量。信号组合器的输出耦合到峰值检测器，该峰值检测器选择最小的基于距离的“去偏置”输出作为发送的码字。

47. 发明公开

EP1065711A2 Method of manufacturing a plated electronic termination 审中-公开
标题翻译：制造镀层电子端子的方法
公开(公告)号：EP1065711A2
公开(公告)日：2001-01-03
申请号：EP00109592.6
申请日：2000-05-05
申请人： Intersil Corporation
发明人： Kwoka, Mark , Linn, Jack
IPC分类号： H01L21/48 , H01L23/495
CPC分类号： H01L23/49582 , H01L21/4842 , H01L24/48 , H01L24/97 , H01L2224/48247 , H01L2224/85464 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , Y10T29/49121 , Y10T29/49204 , Y10T29/49211 , Y10T29/49218 , Y10T29/49224 , H01L2224/45099 , H01L2924/00
摘要： A method of making a lead finish incorporating mechanically flattening the plated coating of metal leads. This may be accomplished by mechanical means such as rolling, stamping, peening, coining, forging.
摘要翻译：一种制造引线精加工的方法，其包含机械平坦化金属引线的镀覆涂层。这可以通过机械手段如轧制，冲压，喷丸，压印，锻造来完成。

48. 发明公开

EP1065708A2 Silicon wafer cleaning process for post-chemical mechanical polishing using immersion 审中-公开
标题翻译：一种用于通过Eintäuschen用于化学机械抛光的方法清洗硅衬底的方法
公开(公告)号：EP1065708A2
公开(公告)日：2001-01-03
申请号：EP00104706.7
申请日：2000-03-03
申请人： Intersil Corporation
发明人： Hackenberg, Diana
IPC分类号： H01L21/306
CPC分类号： H01L21/02052 , Y10S134/902
摘要： A method for removing a slurry from a silicon wafer after chemical-polishing in which the wafer is subjected to at least 2 or more chemical megasonic baths for a short duration of time. The pH of the first megasonic bath matches the pH of the slurry to be removed.
摘要翻译：一种用于化学 - 抛光后从硅晶片中除去浆料的方法，其中所述晶片进行至少两个或更多个化学兆声波浴的时间短的持续时间。第一兆声波浴的pH相匹配待除去的浆料的pH值。

49. 发明公开

EP1058317A2 Low voltage dual-well MOS device 有权
标题翻译：低电压MOS器件和相应的制造方法
公开(公告)号：EP1058317A2
公开(公告)日：2000-12-06
申请号：EP00401471.8
申请日：2000-05-25
申请人： Intersil Corporation
发明人： Zeng, Jun , Wheatley, Carl, Jr.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/66712
摘要： A low-voltage MOS device (100) having high ruggedness, low on-resistance, and body diode reverse recovery characteristics comprises a semiconductor substrate (101) on which is disposed a doped upper layer (102) of a first conduction type. The upper layer includes at its upper surface a blanket implant of the first conduction type, a heavily doped source region (113) of the first conduction type, and a heavily doped body region (112) of a second and opposite conduction type. The upper layer further includes a doped first well region (108) of the first conduction type and a doped well region (109) of the second conduction type underlying the source and body regions. The first well region (108) underlies the second well region (109) and merges with the blanket implant to form a heavily doped neck region that abuts the second well region at the upper surface of the upper layer. A gate comprising a conductive material separated from the upper layer by an insulating layer is disposed on the upper layer overlying the heavily doped neck region.

50. 发明公开

EP1033759A3 MOS-gated device having a buried gate and process for forming same 有权
标题翻译：具有掩埋栅极的MOS栅器件及其形成过程
公开(公告)号：EP1033759A3
公开(公告)日：2000-11-22
申请号：EP00102398.5
申请日：2000-02-03
申请人： Intersil Corporation
发明人： Kocon, Christopher , Zeng, Jun
IPC分类号： H01L29/78 , H01L29/739 , H01L29/74 , H01L21/336 , H01L21/331 , H01L21/332
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66348 , H01L29/66734 , H01L29/7397
摘要： An improved trench MOS-gated device (200) comprises a monocrystalline semiconductor substrate (201) on which is disposed a doped upper layer (202). The upper layer includes at an upper surface (214) a plurality of heavily doped body regions having a first polarity and overlying a drain region (203). The upper layer further includes at its upper surface a plurality of heavily doped source regions (206) having a second polarity opposite that of the body regions. A gate trench (207) extends from the upper surface of the upper layer to the drain region (203) and separates one source region from another. The trench (207) has a floor (209) and sidewalls (208) comprising a layer of dielectric material and contains a conductive gate material (210) filled to a selected level and an isolation layer of dielectric material (212) that overlies the gate material and substantially fills the trench. The upper surface (213) of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface (214) of the upper layer (202). A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.
摘要翻译：改进的沟槽MOS栅器件（200）包括其上设置有掺杂上层（202）的单晶半导体衬底（201）。上层在上表面（214）处包括具有第一极性并且覆盖漏极区（203）的多个重掺杂本体区。上层还在其上表面包括多个具有与本体区域相反的第二极性的重掺杂源极区域（206）。栅极沟槽（207）从上层的上表面延伸到漏极区域（203）并且将一个源极区域与另一个源极区域分开。沟槽（207）具有地板（209）和侧壁（208），侧壁（208）包括介电材料层并且包含填充到选定水平面的导电栅极材料（210）和介电材料隔离层（212）材料并充分填充沟槽。沟槽中上覆的介电材料层的上表面（213）因此基本上与上层（202）的上表面（214）共面。用于形成改进的MOS栅极器件的工艺提供了一种器件，其栅极沟槽用导电栅极材料填充到选定的水平，其上形成有隔离介质层，该隔离介质层的上表面基本上与上层的上表面共面的设备。

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