专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

EP1072105B1 WIRELESS LOCAL AREA NETWORK SPREAD SPECTRUM TRANSCEIVER WITH MULTIPATH INTERFERENCE MITIGATION 有权
标题翻译：无线局域网扩展频谱收发器，具有多径干扰缓解
公开(公告)号：EP1072105B1
公开(公告)日：2004-07-28
申请号：EP99904097.5
申请日：1999-01-15
申请人： Intersil Corporation
发明人： ANDREN, Carl , WEBSTER, Mark, A.
IPC分类号： H04B1/707 , H04L25/03
CPC分类号： H04L27/2332 , H04B1/707 , H04B1/709 , H04B7/08 , H04B7/0811 , H04L25/03057 , H04L25/03267 , H04L27/2273 , H04L2025/03401 , H04L2025/0349 , H04W84/12 , H04W88/02

42. 发明公开

EP1052690A3 Process or forming MOS-gated devices having self-aligned trenches 审中-公开
标题翻译：一种用于与MOS栅极器件和自对准沟槽的制造过程
公开(公告)号：EP1052690A3
公开(公告)日：2003-12-03
申请号：EP00108965.5
申请日：2000-04-27
申请人： Intersil Corporation
发明人： Grebs, Thomas
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/7813
摘要： A process for forming an MOS-gated device having sell-aligned trenches, a screen oxide layer is formed on an upper layer of a semiconductor substrate, and a nitride layer is formed on the screen oxide layer. Using a well mask, the nitride layer is patterned and etched to define a well region in the upper layer, and ions of a first conduction type are diffused into the masked upper layer to form the well region. Ions of a second, opposite conduction type are implanted into the well region of the masked upper layer to form a source region extending to a selected depth that defines a source-well junction. The well mask is removed, exposing the portion of the nitride layer previously underlying the mask. An oxide insulating layer providing a hard mask is formed overlying the well and source regions in the upper layer. The remaining portions of the nitride layer and the screen oxide layer underlying it, which had been protected by the well mask, are removed, exposing the portion of the substrate not masked by the oxide insulating layer. The portion of the substrate thus exposed is etched to form a gate trench extending through the substrate to a selected depth beneath the well region. Sidewalls and a floor of an insulator are formed in the gate trench, which is filled with a semiconductor. The semiconductor in the trench is planarized to be substantially coplanar with the upper surface of the oxide insulating layer. An interlevel dielectric layer is formed on the planarized gate trench semiconductor and the upper surface of the oxide insulating layer.

43. 发明公开

EP1128566A3 Biased-corrected rake receiver for direct sequence spread spectrum waveform 审中-公开
标题翻译：零Direktsequenzspreizspektrumwellenform更正RAKE接收机
公开(公告)号：EP1128566A3
公开(公告)日：2003-10-01
申请号：EP01101976.7
申请日：2001-01-29
申请人： Intersil Corporation
发明人： Webster, Mark , Nelson, George , Halford, Steven
IPC分类号： H04B1/707
CPC分类号： H04B1/7115 , H04B1/7093
摘要： The performance of a RAKE receiver for indoor multipath WLAN applications on direct sequence spread spectrum signals having relatively short codeword lengths comprises a channel-matched filter and codeword correlator front end, plus a signal combiner to which the codeword correlation component is applied. The signal combiner is supplied with a bias-corrected input calculated by a distorted codeword signature (power) generator, which is operative to generate and store a set of N codeword power correction values. The signal combiner combines correction values into the codeword correlation for each potentially transmitted codeword S k . This serves to correct each correlation codeword metric by a de-biasing power component |S k | 2 for the unequal multipath-based distortions of the codeword energies. The output of the signal combiner is coupled to a peak detector, which selects a minimum distance-based 'de-biased' output as the transmitted codeword.

44. 发明公开

EP1065727A3 Edge termination for silicon power devices 有权
标题翻译：硅功率器件边缘终端
公开(公告)号：EP1065727A3
公开(公告)日：2003-05-02
申请号：EP00401826.3
申请日：2000-06-27
申请人： Intersil Corporation
发明人： Zeng, Jun , Dolry, Gary , Muraleedharan, Praveen
IPC分类号： H01L29/06
CPC分类号： H01L29/0615 , H01L29/1608 , H01L29/267 , Y10S438/931
摘要： A silicon semiconductor die comprises a heavily doped silicon substrate (701) and an upper layer (702) comprising doped silicon of a first conduction type disposed on the substrate (701). The upper layer comprises a well region (703) of a second, opposite conduction type adjacent an edge termination zone (705) that comprises a layer of a material having a higher critical electric field than silicon. Both the well region (703) and adjacent edge termination zone (705) are disposed at an upper surface of the upper layer, and an oxide layer (706) overlies the upper layer and the edge termination zone. The invention also concerns a process for forming a silicon die having edge termination.

45. 发明公开

EP1058317A3 Low voltage dual-well MOS device 有权
标题翻译： MOS Bauelement mit Doppelwannefürniedrige Spannungen
公开(公告)号：EP1058317A3
公开(公告)日：2002-11-13
申请号：EP00401471.8
申请日：2000-05-25
申请人： Intersil Corporation
发明人： Zeng, Jun , Wheatley, Carl, Jr.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/36 , H01L29/08
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/66712
摘要： A low-voltage MOS device (100) having high ruggedness, low on-resistance, and body diode reverse recovery characteristics comprises a semiconductor substrate (101) on which is disposed a doped upper layer (102) of a first conduction type. The upper layer includes at its upper surface a blanket implant of the first conduction type, a heavily doped source region (113) of the first conduction type, and a heavily doped body region (112) of a second and opposite conduction type. The upper layer further includes a doped first well region (108) of the first conduction type and a doped well region (109) of the second conduction type underlying the source and body regions. The first well region (108) underlies the second well region (109) and merges with the blanket implant to form a heavily doped neck region that abuts the second well region at the upper surface of the upper layer. A gate comprising a conductive material separated from the upper layer by an insulating layer is disposed on the upper layer overlying the heavily doped neck region.
摘要翻译：具有高耐久性，低导通电阻和改善的体二极管反向恢复特性的改进的低电压MOS器件包括其上设置有第一导电类型的掺杂上层的半导体衬底。上层在其上表面包括第一导电类型的覆盖注入，第一导电类型的重掺杂源区和第二和相反导电类型的重掺杂体区。上层还包括第一导电类型的掺杂的第一阱区和位于源极和体区的第二导电类型的掺杂阱区。第一阱区域位于第二阱区域的下面，并与橡皮布植入物合并以形成与上层的上表面邻接第二阱区域的重掺杂的颈区域。包括通过绝缘层从上层分离的导电材料的门设置在覆盖重掺杂颈部区域的上层上。一种用于形成具有高耐久性，低导通电阻和改善的体二极管反向恢复特性的改进的低电压MOS器件的方法包括提供包括第一导电类型的掺杂上层的半导体衬底，以及在上层的上表面中的第一导电类型。在衬底的上层上形成包括导电材料和绝缘层的栅极，并且通过注入第一导电类型的掺杂的第一阱区和第二导电类型和第二导电类型的掺杂的第二阱区，第一和第二导电类型通过共同的窗口进入上层的上表面。第一阱区域位于第二阱区域的下方并且与橡皮布注入合并，形成在栅极下方的重掺杂的颈部区域并且邻接上层的上表面处的第二阱区域。在上层的上表面处的第二阱区中形成第一导电类型的重掺杂源区和第二导电类型的重掺杂体区。

46. 发明公开

EP1089537A2 Line circuit apparatus for supplying power to a telephone set in telecommunication systems 审中-公开
标题翻译：一种用于在通信系统中的电话的电源用户线设备
公开(公告)号：EP1089537A2
公开(公告)日：2001-04-04
申请号：EP00402138.2
申请日：2000-07-26
申请人： Intersil Corporation
发明人： Youngblood, Douglas
IPC分类号： H04M19/00 , H04M19/02
CPC分类号： H04M19/005 , Y10T307/398
摘要： A subscriber line interface circuit ("SLIC") (10) for a telecommunications device powered from a single power source (20) and using a voltage regulator (16) to limit the voltage across the terminals of the telecommunications device to a predetermined value below the industry standard voltage limits. The SLIC (10) selectively enables or disables the speech amplifiers (120, 126) responsive to an external control signal (22) that is independent of the on-hook / off-hook status of the telecommunications device. The SLIC (10) provides a ringing signal and / or a caller identification signal through the speech amplifiers to the telecommunications device while the telecommunications device is on-hook.

47. 发明公开

EP1066691A2 METHOD OF PERFORMING ANTENNA DIVERSITY IN SPREAD SPECTRUM IN WIRELESS LOCAL AREA NETWORK 审中-公开
标题翻译：天线分集的执行程序在无线局域网网络SPECTRUM GESPREITZTEM
公开(公告)号：EP1066691A2
公开(公告)日：2001-01-10
申请号：EP99904096.7
申请日：1999-01-15
申请人： Intersil Corporation
发明人： FAKATSELIS, John , LUCAS, Leonard, V.
IPC分类号： H04B7/08
CPC分类号： H04L27/2332 , H04B1/707 , H04B1/709 , H04B7/08 , H04B7/0811 , H04L25/03057 , H04L25/03267 , H04L27/2273 , H04L2025/03401 , H04L2025/0349 , H04W84/12 , H04W88/02
摘要： A method of performing antenna diversity in a wireless spread spectrum communication system is disclosed. A spread spectrum phase shift keyed (PSK) packet signal having data symbols formed from high rate mode chips is received in each of two respective spaced antenna of a spread spectrum receiver. The bit sync peak sample is determined within the packet signal for each antenna. Predetermined bit sync samples are subtracted a predetermined number of chips on either side of the bit sync peak sample from the peak for each antenna. The antenna having the higher value obtained in the subtracting step accomplished for each antenna is selected.

48. 发明公开

EP1065715A2 Bicmos process with low temperature coefficient resistor (TCRL) 审中-公开
标题翻译： BiCMOS工艺具有低温度系数电阻器
公开(公告)号：EP1065715A2
公开(公告)日：2001-01-03
申请号：EP00401889.1
申请日：2000-06-30
申请人： Intersil Corporation
发明人： Hemmenway, Donald , Delgado, John , Butler, John , Rivoli, Anthony
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L28/20 , H01L21/763 , H01L21/8249 , H01L27/0635
摘要： A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.

49. 发明公开

EP1065707A1 Integrated high and low resistance contacts 审中-公开
标题翻译： Integrierte Kontakte mit hohem und niedrigem Wiederstand
公开(公告)号：EP1065707A1
公开(公告)日：2001-01-03
申请号：EP00104714.1
申请日：2000-03-03
申请人： Intersil Corporation
发明人： Woodbury, Dustin , Czagas, Joseph
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L27/11
CPC分类号： H01L28/20 , H01L21/28512 , H01L21/28518 , Y10S257/914
摘要： A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling species such as carbon or oxygen are implanted into all contacts. The high resistive contacts are covered with a barrier metal to protect suicide from chemical interaction with the interconnect metalization (aluminum) in the low-resistance contacts. Selective suicide formation converts some of the contacts back to low-resistance contacts.
摘要翻译：半导体器件或集成电路具有高和低电阻触点。移动性破坏物质如碳或氧被植入所有触点。高电阻触点覆盖有阻挡金属，以保护自杀与低电阻触点中的互连金属化（铝）的化学相互作用。选择性自杀形成将一些触点转换回低电阻触点。

50. 发明公开

EP1065706A2 Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide 审中-公开
标题翻译：一种用于在一个由厚氧化物层晶片的装置相关联的底部产生一个扩散层过程
公开(公告)号：EP1065706A2
公开(公告)日：2001-01-03
申请号：EP00111199.6
申请日：2000-05-24
申请人： Intersil Corporation
发明人： Czagas, Joseph , Woodbury, Dustin , Beasom, James
IPC分类号： H01L21/225 , H01L21/762 , H01L21/18 , H01L21/265 , H01L29/10 , H01L29/78
CPC分类号： H01L21/2253 , H01L21/187 , H01L21/2007 , H01L21/2255 , H01L21/2256 , H01L21/26513 , H01L21/74 , H01L21/76251 , H01L29/0615 , H01L29/10 , H01L29/1079 , H01L29/1083 , Y10S438/933
摘要： Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and a deposited oxide.
摘要翻译：集成电路，半导体器件及其制造方法相同的方法进行了描述。每个实施例中示出了在器件晶片的扩散，掺杂背面层确实是氧化键合到一个处理晶片。扩散层可以起源于器件晶片，在处理晶片，在键合氧化物或多晶硅或外延硅的附加的半导体层。该方法使用热粘型氧化物或热和淀积氧化物的组合。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式