专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1065727A2 Edge termination for silicon power devices 有权
标题翻译： RandabschlussfürSilizium-Leistungsanordnungen
公开(公告)号：EP1065727A2
公开(公告)日：2001-01-03
申请号：EP00401826.3
申请日：2000-06-27
申请人： Intersil Corporation
发明人： Zeng, Jun , Dolry, Gary , Muraleedharan, Praveen
IPC分类号： H01L29/06
CPC分类号： H01L29/0615 , H01L29/1608 , H01L29/267 , Y10S438/931
摘要： A silicon semiconductor die comprises a heavily doped silicon substrate (701) and an upper layer (702) comprising doped silicon of a first conduction type disposed on the substrate (701). The upper layer comprises a well region (703) of a second, opposite conduction type adjacent an edge termination zone (705) that comprises a layer of a material having a higher critical electric field than silicon. Both the well region (703) and adjacent edge termination zone (705) are disposed at an upper surface of the upper layer, and an oxide layer (706) overlies the upper layer and the edge termination zone. The invention also concerns a process for forming a silicon die having edge termination.
摘要翻译：硅半导体管芯包括重掺杂硅衬底（701）和包括设置在衬底（701）上的第一导电类型的掺杂硅的上层（702）。上层包括邻近边缘终止区（705）的第二相反导电类型的阱区（703），其包括具有比硅更高的临界电场的材料层。阱区域（703）和相邻的边缘终止区域（705）均设置在上层的上表面，并且氧化物层（706）覆盖在上层和边缘终止区域上。本发明还涉及一种用于形成具有边缘终止的硅片的方法。

2. 发明授权

EP1065727B1 Edge termination for silicon power devices 有权
标题翻译：硅功率器件边缘终端
公开(公告)号：EP1065727B1
公开(公告)日：2006-05-24
申请号：EP00401826.3
申请日：2000-06-27
申请人： Intersil Corporation
发明人： Zeng, Jun , Dolry, Gary , Muraleedharan, Praveen
IPC分类号： H01L29/06
CPC分类号： H01L29/0615 , H01L29/1608 , H01L29/267 , Y10S438/931

3. 发明公开

EP1065727A3 Edge termination for silicon power devices 有权
标题翻译：硅功率器件边缘终端
公开(公告)号：EP1065727A3
公开(公告)日：2003-05-02
申请号：EP00401826.3
申请日：2000-06-27
申请人： Intersil Corporation
发明人： Zeng, Jun , Dolry, Gary , Muraleedharan, Praveen
IPC分类号： H01L29/06
CPC分类号： H01L29/0615 , H01L29/1608 , H01L29/267 , Y10S438/931
摘要： A silicon semiconductor die comprises a heavily doped silicon substrate (701) and an upper layer (702) comprising doped silicon of a first conduction type disposed on the substrate (701). The upper layer comprises a well region (703) of a second, opposite conduction type adjacent an edge termination zone (705) that comprises a layer of a material having a higher critical electric field than silicon. Both the well region (703) and adjacent edge termination zone (705) are disposed at an upper surface of the upper layer, and an oxide layer (706) overlies the upper layer and the edge termination zone. The invention also concerns a process for forming a silicon die having edge termination.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式