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31. 发明公开

EP0186958A2 Digital data processor for matrix-vector multiplication 有权转让
标题翻译：为矩阵 - 向量乘法的数字数据处理器。
公开(公告)号：EP0186958A2
公开(公告)日：1986-07-09
申请号：EP85308310.3
申请日：1985-11-14
申请人： NATIONAL RESEARCH DEVELOPMENT CORPORATION
发明人： Ward, Jeremy
IPC分类号： G06F7/52 , G06F15/76 , G06F15/332
CPC分类号： G06F17/16 , G06F7/525 , G06F15/8046 , G06F17/15 , G06F2207/3884
摘要： A digital data processor for matrix-vector multiplication is provided, and comprises a systolic array (10) of bit-level, synchronously clock activated processing cells (12) each connected to its row and column neighbours. On each clock cycle, each cell (12) multiplies an input bit of a respective vector coefficient by a respective matrix coefficient equal to +1, -1 or 0, and adds it to cumulative sum and carry input bits. Input vector coefficient bits pass along respective array rows through one cell (12) per clock cycle. Contributions to matrix-vector product bits are accumulated in array columns. Input to and output from the array (10) is bit-serial, word parallel, Isb leading, and temporally skewed. Transforms such as the discrete Fourier transform may be implemented by a two-channel device (150), in which each channel contains two processors of the invention with an intervening bit serial multiplier. Processors of the invention may be replicated to implement multuplication by larger matrices.

32. 发明公开

EP0169010A2 Systolic array for solving cyclic loop dependent algorithms 失效
标题翻译：脉动阵列与循环回路解决算法。
公开(公告)号：EP0169010A2
公开(公告)日：1986-01-22
申请号：EP85304753.8
申请日：1985-07-03
申请人： LORAL AEROSPACE CORPORATION
发明人： Parvin, Bahram Alizadeh
IPC分类号： G06F15/76
CPC分类号： G06F15/8046
摘要： A systolic array (1) for reducing the time required to solve an algorithm having cyclic loop dependency, i.e., nested loops in which values calculated by inner loops depend upon indices of said inner loops and upon indices of outer loops. The array (1) comprises a chain of several identical sequentially connected cells. In the preferred embodiment, each cell, except for first and last cells in the chain, is connected to its two adjacent cells only. Multiprocessing is employed: at certain times during the algorithm solving, more than one cell is simultaneously activated to perform portions of the solving, so that the total time required to solve the algorithms is shortened to be a linear function of n and m. The algorithm can represent measurement of the distance between two symbolic strings, or other problems in artificial intelligence or logic. The algorithm is broken up into nm subalgorithms D(i,j); at each processing step, those subalgorithms D(i,j) are solved for which sufficient informations exists for their solution. In the illustrated example, this condition is represented by diagonally time-slicing a two-dimensional matrix having as elements each of the subalgorithms D(i,j).

33. 发明公开

EP0144123A2 Digital data processor for multiplying data elements by coefficients 失效
标题翻译：相乘数据元素和系数的数字数据处理器。
公开(公告)号：EP0144123A2
公开(公告)日：1985-06-12
申请号：EP84306215.9
申请日：1984-09-10
申请人： NATIONAL RESEARCH DEVELOPMENT CORPORATION
发明人： McCanny, John Vincent Dept. of Elect. & Electronic , McWhirter, John Graham , Wood, Kenneth William
IPC分类号： G06F15/347
CPC分类号： G06F15/8046 , G06F17/15
摘要： A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array (70) of cells (71) consisting of nearest neighbour connected gated full adders. The cells (71) multiply data bits received from laterally adjacent cells (70) and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell (71) below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array (70). An adder tree (110) accumulates non-simultaneously computed contributions to individual output terms. The tree (110) incorporates a delay (122) and switches (120, 121) arranged to implement or bypass the delay (122) according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

34. 发明公开

EP4413469A1 RECHENVORRICHTUNG, VERFAHREN ZUR LASTVERTEILUNG FÜR EINE SOLCHE RECHENVORRICHTUNG UND COMPUTERSYSTEM 审中-实审
公开(公告)号：EP4413469A1
公开(公告)日：2024-08-14
申请号：EP23773217.7
申请日：2023-09-18
申请人： Mercedes-Benz Group AG
发明人： WILMER, Thorsten
IPC分类号： G06F15/80 , G06F15/82 , G06F15/167
CPC分类号： G06F15/8023 , G06F15/825 , G06F15/8046 , G06F15/167

35. 发明公开

EP4359919A1 DUAL PIPELINE PARALLEL SYSTOLIC ARRAY 审中-实审
公开(公告)号：EP4359919A1
公开(公告)日：2024-05-01
申请号：EP22714700.6
申请日：2022-03-16
申请人： Intel Corporation
发明人： PARRA, Jorge , CHEN, Jiasheng , PAL, Supratim , FU, Fangwen , GANAPATHY, Sabareesh , GURRAM, Chandra , MEI, Chunhui , QI, Yue
IPC分类号： G06F9/30 , G06F9/38 , G06F17/16 , G06F15/80
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30036 , G06F9/3893 , G06F9/3828 , G06F17/16 , G06F15/8046

36. 发明公开

EP3407203A2 STATICALLY SCHEDULABLE FEED AND DRAIN STRUCTURE FOR SYSTOLIC ARRAY ARCHITECTURE 有权
公开(公告)号：EP3407203A2
公开(公告)日：2018-11-28
申请号：EP18163741.4
申请日：2018-03-23
申请人： INTEL Corporation
发明人： HUANG, Randy , LIEW, Yeong Tat , ONG, Jason Gee Hock
IPC分类号： G06F17/16
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0673 , G06F5/065 , G06F5/08 , G06F5/14 , G06F7/523 , G06F15/76 , G06F15/8046 , G06F17/16 , G06F2205/067 , G06F2205/126
摘要： A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.

37. 发明公开

EP3373152A1 VECTOR PROCESSING UNIT 审中-实审
公开(公告)号：EP3373152A1
公开(公告)日：2018-09-12
申请号：EP17199241.5
申请日：2017-10-30
申请人： Google LLC
发明人： LACY, William , THORSON, Gregory Michael , CLARK, Christopher Aaron , JOUPPI, Norman Paul , NORRIE, Thomas , PHELPS, Andrew Everett
IPC分类号： G06F15/80 , G06T1/20
CPC分类号： G06F9/3001 , G06F7/588 , G06F9/30036 , G06F9/30043 , G06F9/30098 , G06F13/36 , G06F13/4068 , G06F13/4282 , G06F15/8046 , G06F15/8053 , G06F15/8092 , G06F17/16 , G06N3/063
摘要： A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

38. 发明公开

EP3298546A1 PREFETCHING WEIGHTS FOR USE IN A NEURAL NETWORK PROCESSOR 有权
标题翻译：预选权重用于神经网络处理器
公开(公告)号：EP3298546A1
公开(公告)日：2018-03-28
申请号：EP16725266.7
申请日：2016-04-29
申请人： Google LLC
发明人： ROSS, Jonathan
IPC分类号： G06N3/02 , G06N3/063 , G06F15/80
CPC分类号： G06N3/063 , G06F15/8046
摘要： A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers: shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry.

39. 发明公开

EP3066579A1 COMPUTING ARCHITECTURE FOR OPERATING ON SEQUENTIAL DATA 审中-公开
标题翻译： BERECHNUNGSARCHITEKTURFÜRSEQUENTILELE DATEN
公开(公告)号：EP3066579A1
公开(公告)日：2016-09-14
申请号：EP14805708.6
申请日：2014-10-31
申请人： Lewis Rhodes Labs, Inc.
发明人： FOLLETT, David , FOLLETT, Pamela, L.
IPC分类号： G06F15/80
CPC分类号： G06F15/82 , G06F15/8046
摘要： A data stream processing unit (DPU) and method for use are provided. A DPU includes a number of processing elements arranged in a sequence, and each datum in the data stream visits each processing element in sequence. Each processing element has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. The computing circuit for each processing element operates on the data and metadata inputs as a function of its position in the sequence, producing an altered partial computational state that accompanies the datum. Each computing circuit may be modeled, for example, as a finite state machine, and the collection of processing elements cooperate to perform the computation. The computing circuits may be collectively programmed to perform any desired computation.
摘要翻译：提供了一种数据流处理单元（DPU）及其使用方法。 DPU包括以序列排列的多个处理元件，并且数据流中的每个数据顺序地访问每个处理元件。每个处理元件具有存储器电路，数据和元数据输入和输出通道，以及计算电路。元数据输入表示在通过DPU时与每个数据相关联的部分计算状态。用于每个处理元件的计算电路作为其在该序列中的位置的函数对数据和元数据输入进行操作，产生伴随该数据的改变的部分计算状态。每个计算电路可以被建模为例如有限状态机，并且处理元件的集合协作来执行计算。计算电路可以被集体编程以执行任何期望的计算。

40. 发明授权

EP2504962B1 MIMO MINIMUM MEAN SQUARE ERROR RECEIVER USING QR DECOMPOSITION AND SYSTOLIC ARRAYS 有权
标题翻译： MIMO最小AVERAGING方误差接收机QR切割和脉动阵列
公开(公告)号：EP2504962B1
公开(公告)日：2016-05-18
申请号：EP10735159.5
申请日：2010-07-20
申请人： Xilinx, Inc.
发明人： MAZAHREH, Raied, N. , TARN, Hai-Jo , RAO, Raghavendar, M.
IPC分类号： H04L25/02 , G06F15/80 , G06F17/16
CPC分类号： G06F17/16 , G06F7/78 , G06F15/8046 , H04B7/0413 , H04B7/0854 , H04L25/0244

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