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21. 发明授权

EP2278474B8 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
公开(公告)号：EP2278474B8
公开(公告)日：2015-10-21
申请号：EP10178677.0
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.

22. 发明授权

EP2192494B1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2192494B1
公开(公告)日：2012-06-20
申请号：EP10150033.8
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16 , G11C29/02
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.

23. 发明公开

EP2192494A1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2192494A1
公开(公告)日：2010-06-02
申请号：EP10150033.8
申请日：2002-04-23
申请人： RAMBUS INC.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

24. 发明公开

EP1253521A3 Method and apparatus for signaling between devices of a memory system 有权
标题翻译：对存储系统的设备之间的信令的方法和装置
公开(公告)号：EP1253521A3
公开(公告)日：2006-12-13
申请号：EP02009031.2
申请日：2002-04-23
申请人： RAMBUS INC.
发明人： Ware, Frederick A. , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F13/1689 , G11C29/02 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.

25. 发明公开

EP1291778A3 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP1291778A3
公开(公告)日：2005-08-17
申请号：EP02009032.0
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick A. , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G06F13/1689 , G11C29/02 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

26. 发明公开

EP1253521A2 Method and apparatus for signaling between devices of a memory system 有权
标题翻译： Verfahren und Vorrichtung zur Signalisierung zwischenGeräteneines Speichersystems
公开(公告)号：EP1253521A2
公开(公告)日：2002-10-30
申请号：EP02009031.2
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick A. , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/42 , G06F13/16
CPC分类号： G06F13/1689 , G11C29/02 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.
摘要翻译：提供了一种用于在存储器系统的设备之间进行信令的方法和装置。根据本发明的实施例，实现了几个能力中的一个或多个，以提供迄今为止无法达到的重要系统度量的水平，例如高性能和/或低成本。这些功能涉及定时调整能力，位时间调整能力，周期时间选择，对总线信号和/或时钟信号的差分和/或非差分信号的使用，在总线上使用终端结构，包括集成终端结构，以及主动控制电路，以允许调整不同的特性总线阻抗和功率状态控制，包括优化终端值的校准过程，使用压摆率控制电路和传输特征控制电路在发射机模块的预驱动器和驱动器中，以允许调整不同的特性总线阻抗，并且允许调整其他总线属性，包括优化这种电路的校准过程，和/或提供设计成预先获取（预访问）字的存储器组件，其比数据总线的宽度宽，使得存储器访问带宽近似匹配传输带宽和备忘录 ry组件能够调整预取（预访问）字的大小，以适应与不同宽度的数据总线的连接。

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