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21. 发明公开

EP0550286A3 2-Level multi-processor synchronization protocol 失效
标题翻译： 2级多处理器同步协议
公开(公告)号：EP0550286A3
公开(公告)日：1993-11-03
申请号：EP92311898.8
申请日：1992-12-31
申请人： AMDAHL CORPORATION
发明人： Magee, Stephen C. , Lipman, Peter H.
IPC分类号： G06F9/46 , G06F11/34 , G06F9/44
CPC分类号： G06F9/4843 , G06F9/463
摘要： A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.

22. 发明公开

EP0550289A2 A mechanism to detect stores into the instruction stream 失效
标题翻译：机构Befehlsstrom的机构zur Entdeckung von Speicherbefehlen。
公开(公告)号：EP0550289A2
公开(公告)日：1993-07-07
申请号：EP92311902.8
申请日：1992-12-31
申请人： AMDAHL CORPORATION
发明人： Munson, Kenneth Kroymann , Taylor, Michael Demar
IPC分类号： G06F9/38
CPC分类号： G06F9/3812
摘要： A pipeline computer executes instructions in a plurality of pipeline segments where some instructions store into the instruction stream (STIS) STIS operations are detected and the pipeline is purged to avoid the use by the computer system of incorrect data. Detection of a STIS operation is done by comparing the current instruction address (CIA) to the next sequential instruction address (NSIA). A STIS address register (STAR) identifies addresses of all instructions in the pipeline. Although the STAR address is near to the NSIA, it does not necessarily match the next sequential instruction address. The STAR address is compared with the NSIA and performance is enhanced since not until the NSIA has been incremented to overlap the STAR address is a STIS condition is reported.
摘要翻译：流水线计算机执行多个流水线段中的指令，其中某些指令存储到指令流（STIS）中，检测到STIS操作，并清除流水线以避免计算机系统使用不正确的数据。通过将当前指令地址（CIA）与下一个顺序指令地址（NSIA）进行比较来完成STIS操作的检测。 STIS地址寄存器（STAR）标识所有指令的地址。虽然STAR地址靠近NSIA，但它不一定与下一个顺序指令地址相匹配。 STAR地址与NSIA进行比较，性能得到增强，因为直到NSIA已经增加到与STAR地址重叠是STIS条件被报告。

23. 发明公开

EP0414729A1 A FILE SYSTEM FOR A PLURALITY OF STORAGE CLASSES 有权
标题翻译：文件系统存储类的品种。
公开(公告)号：EP0414729A1
公开(公告)日：1991-03-06
申请号：EP89904939.0
申请日：1989-04-19
申请人： AMDAHL CORPORATION
发明人： KRAKAUER, Arno, Starr , GAWLICK, Dieter , COLGROVE, John Alan , WILMOT, Richard, Byron, II
IPC分类号： G06F3 , G06F9 , G06F11 , G06F12 , G06F15 , G06F17
CPC分类号： G06F11/2089 , G06F9/50 , G06F11/1008 , G06F11/201 , G06F11/2056 , G06F11/2094 , G06F12/08 , G06F15/161 , G06F17/30067 , Y10S707/99953
摘要： Un système de fichiers permettant la gestion de fichiers de données auxquels ont accès une pluralité d'utilisateurs d'un système informatique, comprend un stockage interne (41) permettant la mise en mémoire tampon, un stockage externe (44), ainsi qu'une interface (I) d'utilisateur de fichiers au moyen de laquelle la pluralité d'utilisateurs demandent l'accès aux fichiers de données. Un premier niveau est couplé à l'interface (41) d'utilisateurs de fichiers afin de stocker des données temporairement auxquelles ont accès une pluralité d'utilisateurs. Un second niveau est couplé au premier niveau et au stockage externe (44), et répond à la demande de transactions avec le stockage externe (44) afin de gérer les transactions en vue de procéder au stockage de données dans ledit stockage externe (44) et à la récupération de données à partir de ce dernier.

24. 发明公开

EP0271187A3 Split instruction and operand cache management 失效
标题翻译：分区指令和操作高速缓存管理
公开(公告)号：EP0271187A3
公开(公告)日：1990-04-11
申请号：EP87308811.6
申请日：1987-10-05
申请人： AMDAHL CORPORATION
发明人： Woffinden, Gary A. , Ertl, Robert A. , Thomas, Jeffrey A. , Robinson, Theodore S. , Millar, James P. , Finan, Christopher D. , Petolino, Joseph A., Jr. , Shah, Ajay K. , Wang, Shen H. , Semmelmeyer Mark W.
IPC分类号： G06F12/08
CPC分类号： G06F12/0848
摘要： A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic managment of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

25. 发明公开

EP0265108A3 Cache storage priority 失效
标题翻译：缓存优先
公开(公告)号：EP0265108A3
公开(公告)日：1990-01-31
申请号：EP87308810.8
申请日：1987-10-05
申请人： AMDAHL CORPORATION
发明人： Taylor, Michael D. , Kasrazadeh, Mehrzad , Thomas, Jeffrey A. , Finan, Christopher D. , Petolino, Joseph A., Jr.
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0855 , G06F9/3824 , G06F12/0804
摘要： A data processing machine includes an instruction unit that decodes and organizes a flow of instructions for processing data. In response to certain instructions, the instruction unit generates requests for storage unit resources. In addition, results generated in the instruction unit in response to certain instructions are supplied for storage in the storage unit. The storage unit selects in response to priority logic from competing requests for storage unit resources, including a high speed cache storing data, and a plurality of storage ports for transferring data from the result register to the high speed cache. Each of the storage ports generates requests for access to the high speed cache to transfer the data stored in the respective store ports to the cache. Storage unit priority is determined in part by predicting the fullness of the storage ports.

26. 发明公开

EP0257952A3 Apparatus for detecting and classifying errors in control words 失效
标题翻译：控制字错误检测和分类
公开(公告)号：EP0257952A3
公开(公告)日：1990-01-17
申请号：EP87307261.5
申请日：1987-08-17
申请人： AMDAHL CORPORATION
发明人： Goldman, Gary S. , Semmelmeyer, Mark W.
IPC分类号： G06F11/00 , G06F9/38
CPC分类号： G06F9/3865 , G06F9/3863 , G06F9/3867 , G06F11/0721 , G06F11/0751 , G06F11/0763 , G06F11/10
摘要： In a data processing machine that generates a control word and that includes a plurality of registers connected to receive respective copies of the control word for execution in sections of the data processing machine, the present invention provides an apparatus for detecting an error condition in the execution of the control word. The apparatus detects an error in any of the respective copies of the control word. Further, a second means, responsive to the one copy of the control word in one register, is included for analyzing the one copy to identify a class of possible errors. Finally, responsive to the detection of an error in any of the respective copies and to the class of possible errors, a signal is generated indicating an error condition.

27. 发明公开

EP0348053A2 Controlling the initiation of logical systems in a data processing system with logical processor facility 失效
标题翻译：在einem Datenverarbeitungssystem mitlogischerProzessormöglichkeit的Startsteuerung von logischen Systemen。
公开(公告)号：EP0348053A2
公开(公告)日：1989-12-27
申请号：EP89305542.6
申请日：1989-06-01
申请人： AMDAHL CORPORATION
发明人： Mohan, Ram P. , Weber, Ronald
IPC分类号： G06F9/46 , G06F15/16
CPC分类号： G06F9/4843 , G06F9/468 , G06F15/177
摘要： In a computer system that has one or more primary processing units processing user tasks and at least one auxiliary processing unit servicing the primary processing units, feature control is performed by storing a authorization code in the auxiliary processing unit. When an operation to change the feature of the computer system is initiated, a signal, including a key code, is sent to the auxiliary processing unit. The auxiliary processing unit checks the key code against the authorization code, and enables the operation if the check is successful.
摘要翻译：在具有处理用户任务的一个或多个主处理单元的计算机系统和至少一个辅助处理单元服务于主处理单元的情况下，通过在辅助处理单元中存储授权码来执行特征控制。当开始改变计算机系统的特征的操作时，将包括密钥码的信号发送到辅助处理单元。辅助处理单元根据授权码检查密钥代码，如果检查成功，则启用该操作。

28. 发明公开

EP0303783A3 Data processing system with logical processor facitily 有权
标题翻译：具有逻辑处理器的数据处理系统
公开(公告)号：EP0303783A3
公开(公告)日：1989-08-09
申请号：EP88109013.8
申请日：1984-08-17
申请人： AMDAHL CORPORATION
发明人： Lent, Robert Stewart , Willis, Arther Clayton , Doran, Robert William
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/4843 , G06F9/45533 , G06F13/105
摘要： A host computer which functions as one or more variant systems stores one or more system control programs (SCP's) where each SCP is provided for production operation of the host computer. Logical processor means select one of the system control programs for control of the central processing unit. Interrupt routing means operate to match a system control program with a channel operation.

29. 发明公开

EP0143516A3 Multimode scan apparatus 失效
标题翻译：多模式扫描仪
公开(公告)号：EP0143516A3
公开(公告)日：1987-09-16
申请号：EP84305850
申请日：1984-08-28
申请人： AMDAHL CORPORATION
发明人： Si, Stephen S.C. , Merrick, Dale F.
IPC分类号： G06F11/26
CPC分类号： G01R31/318555 , G06F11/2268
摘要： @ Disclosed is a scan apparatus which provides an interface and control signals between a secondary computer and data locations in a host computer. The scan apparatus functions independently of the normal operation of the host computer. Scan-out is performed transparently to the operation of the host computer. The host computer is organized into a plurality of functional units. Each functional unit is constructed of circuits on semiconductor chips. The semiconductor chips are organized in blocks. In the present invention, each block within the host computer includes a multimode scan apparatus which controls the scan operations in connection with that block. The scan apparatus in each block is connected to the secondary computer by clock and scan lines. The scan apparatus on each block includes a multimode sequencer which is controlled by the secondary computer and independently of the operation of the host computer, executes the scan sequences for performing the scan operations associated with the block.

30. 发明公开

EP0157036A2 Serial chip scan 失效
标题翻译： Serienchipabtastung。
公开(公告)号：EP0157036A2
公开(公告)日：1985-10-09
申请号：EP84305851.2
申请日：1984-08-28
申请人： AMDAHL CORPORATION
发明人： Si, Stephen S. C. , Shackleford, James B. , Allred, Daryl H.
IPC分类号： G06F11/26
CPC分类号： G01R31/318558 , G06F11/2268 , G06F11/2733
摘要： Disclosed is a scan apparatus (4) which provides an interface and control signals between a secondary computer (1) and data locations in a host computer (2). The scan apparatus (4) functions independently of the normal operation of the host computer (2). Scan-out is performed transparently to the operation of the host computer (2). The host computer (2) is constructed using circuits on semiconductor chips (7-1, 7-Y). The semiconductor chips (7-1, 7-Y) are organized in blocks (3-1). Chips within each block (3-1) include scan apparatus (4) which controls the scan operations in connection with that chip. The scan apparatus in each chip is connected through two I/O pins to a clock lines and to a bidirectional scan data line. The scan apparatus on each chip includes a multimode sequencer so that each chip in each block can be independently performing scan sequences. The block scan apparatus and the secondary computer perform the functions of requesting a scan sequence for transmitting the scan data.
摘要翻译：公开了一种在辅助计算机（1）和主计算机（2）中的数据位置之间提供接口和控制信号的扫描装置（4）。扫描装置（4）独立于主计算机（2）的正常操作而起作用。对主计算机（2）的操作透明地执行扫描。主计算机（2）使用半导体芯片（7-1.7-Y）上的电路构成。半导体芯片（7-1,7-Y）以块（3-1）组织。每个块（3-1）内的芯片包括扫描装置（4），其控制与该芯片相关的扫描操作。每个芯片中的扫描设备通过两个I / O引脚连接到时钟线和双向扫描数据线。每个芯片上的扫描装置包括多模式定序器，使得每个块中的每个芯片可以独立地执行扫描序列。块扫描装置和辅助计算机执行请求用于发送扫描数据的扫描序列的功能。

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