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11. 发明公开

EP2787508A4 DRIVE CIRCUIT, SHIFT REGISTER, GATE DRIVE, ARRAY SUBSTRATE AND DISPLAY DEVICE 有权
标题翻译：驱动电路的移位寄存器，栅极驱动阵列基板及显示装置
公开(公告)号：EP2787508A4
公开(公告)日：2015-07-15
申请号：EP12790779
申请日：2012-11-09
申请人： BOE TECHNOLOGY GROUP CO LTD , HEFEI BOE OPTOELECTRONICS TECH
发明人： MA RUI , SHAO XIANJIE , WANG GUOLEI , HU MING , LIM BYUNG CHEON , TU ZHIZHONG
IPC分类号： G11C19/28
CPC分类号： G11C19/28 , H03K5/00
摘要： The disclosure relates to the field of liquid crystal display, and provides a driving circuit, a shifting register, a gate driver, an array substrate and a display device. The driving circuit comprises a pull-up module, a first pull-down module, a second pull-down module, a pull-up driving module, a pull-down driving module and a resetting module, wherein the first pull-down module outputs a switching-off signal to the output terminal according to a signal input from the clock retarding signal input terminal and a signal at a pull-down node; a second pull-down module, when the signal input from the signal input terminal is at a low level, outputs a switching-off signal to the pull-up node and the output terminal according to a signal input from a clock signal input terminal; wherein when the signal input from the signal input terminal is at a high level, the signal input from the clock retarding signal input terminal is also at a high level, and the signal input from the clock signal input terminal and that input from the clock retarding signal input terminal are opposite in phase. The driving circuit according to the disclosure can effectively remove the defect of the threshold voltage drifting due to the gate being applied to a bias voltage stress, and can also decrease the noise of the output voltage.

12. 发明公开

EP2779548A1 Isolator-based transmission system with side isolator channel for refresh signals 有权
标题翻译： ISOLATORBASIERTESÜBERTRAGUNGSSYSTEMMIT SEITENISOLATORKANAL ZUR AUFFRISCHUNG VON SIGNALEN
公开(公告)号：EP2779548A1
公开(公告)日：2014-09-17
申请号：EP14157775.9
申请日：2014-03-05
申请人： Analog Devices, Inc.
发明人： Goswami, Bikiran
IPC分类号： H04L25/02 , G06F13/42
CPC分类号： H03K5/00 , G06F13/4221 , H04L25/0266
摘要： A multi-channel isolation system has N+1 isolators for N channels of communication data. N of the isolators may transfer data signals across an isolation barrier, one for each of the N channels of data. An N+1 st isolator transfers refresh signals representing state of the data signals on the N isolators. Receiver circuitry, therefore, may receive signals from the N isolation channels without risk for collision with refresh signals. If reception of the refresh signals becomes necessary, circuitry on a receive side of the isolator may switch over to the N+1 st receive path to output state data contained in the refresh signals.
摘要翻译：多通道隔离系统具有用于N个通道数据通道的N + 1个隔离器。 N个隔离器可以跨越隔离屏障传输数据信号，一个用于N个通道的数据。 N + 1隔离器传送表示N个隔离器上数据信号状态的刷新信号。因此，接收器电路可以从N个隔离通道接收信号，而不会与刷新信号发生冲突。如果需要接收刷新信号，则隔离器的接收侧的电路可以切换到第N + 1个接收路径，以输出包含在刷新信号中的状态数据。

13. 发明公开

EP2698987A1 Noise-resistant sampling circuit and image sensor 审中-公开
标题翻译： RauschbeständigeAbtastschaltung和Bildsensor
公开(公告)号：EP2698987A1
公开(公告)日：2014-02-19
申请号：EP13172218.3
申请日：2013-06-17
申请人： Luxen Technologies, Inc. , Soh, Myung-Jin
发明人： Soh, Myung-Jin , Soh, Seul-Yi
IPC分类号： H04N5/357 , H04N5/363
CPC分类号： H03K5/00 , H04N5/357 , H04N5/3575 , H04N5/378
摘要： An approach for a sampling circuit to reduce noise in signals (e.g., as received from photo diodes or the like) is provided. In one embodiment of the present invention, there is a sampling circuit comprising: an amplifier, which amplifies charge signals generated at photo diodes and converts them to voltage signals; the first sample and hold circuit, which samples the voltage signal and charges the first capacitor according to the first switching signal, and outputs the stored charge as a reset signal based on a readout signal; the second sample and hold circuit, which samples the signals and charges the second capacitor according to the second switching signal that is non-overlapping to the first switching signal, and outputs the stored charge as a reset signal based on the readout signal; a resistor that acts as a low-pass filter placed in between the first and the second capacitors' common nodes.
摘要翻译：提供了一种用于减少信号中的噪声（例如从光电二极管等接收的）的采样电路的方法。在本发明的一个实施例中，有一个采样电路，包括：放大器，其放大在光电二极管处产生的电荷信号并将其转换为电压信号; 第一采样和保持电路，其根据第一开关信号对电压信号进行采样并对第一电容器充电，并且基于读出信号将存储的电荷作为复位信号输出; 第二采样和保持电路，其根据与第一开关信号不重叠的第二开关信号对信号进行采样并对第二电容器充电，并且基于读出信号将存储的电荷作为复位信号输出; 作为放置在第一和第二电容器的公共节点之间的低通滤波器的电阻器。

14. 发明公开

EP2621089A1 DATA PROCESSING METHOD AND DEVICE 无效
标题翻译：数据处理方法和装置
公开(公告)号：EP2621089A1
公开(公告)日：2013-07-31
申请号：EP10857555.6
申请日：2010-09-24
申请人： Shimadzu Corporation
发明人： NODA, Akira
IPC分类号： H03H17/02
CPC分类号： H03K5/00 , H01J49/0036 , H03H17/0294
摘要： For an input signal with a ringing superposed thereon, a ringing-generating filter (12) generates an analogous ringing waveform from only a peak portion of the signal which precedes the ringing. A subtractor (11) subtracts the analogous ringing waveform from the input signal to eliminate the ringing. The coefficient of the filter (12) is determined by applying a calculation method similar to a polynomial division based on the complete pivoting Gaussian elimination to polynomials using a reference data expressing a peak waveform and a ringing waveform, and by using a least squares method for minimizing the square of the covariance so as to allow the presence of noise in the data. Furthermore, by a repetitive process on a plurality of the same datasets, the calculation accuracy of the coefficient is improved even under the condition that the ringing frequency is high and the number of samples in one cycle is small. Thus, the ringing can be correctly eliminated even if the signal frequency is high.
摘要翻译：对于其上叠加了振铃的输入信号，振铃产生滤波器（12）仅从振铃之前的信号的峰值部分产生类似的振铃波形。减法器（11）从输入信号中减去类似的振铃波形以消除振铃。通过使用表示峰值波形和振铃波形的参考数据，并且通过使用最小二乘法来对基于完全枢转高斯消除的多项式除法的计算方法应用于多项式来确定滤波器（12）的系数最小化协方差的平方以便数据中存在噪声。此外，通过对多个相同数据集进行重复处理，即使在振铃频率高并且一个周期中的样本数量小的情况下，系数的计算精度也得到改善。因此，即使信号频率高，也可以正确地消除振铃。

15. 发明公开

EP0030813A2 Boosting circuits 失效
标题翻译： Spannungserhöhungsschaltungen。
公开(公告)号：EP0030813A2
公开(公告)日：1981-06-24
申请号：EP80304344.7
申请日：1980-12-03
申请人： FUJITSU LIMITED
发明人： Nakano, Masao , Baba, Fumio , Mochizuki, Hirohiko
IPC分类号： H03K5/02
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4076 , G11C11/4085 , H03K5/00 , H03K19/00 , H03K19/01707 , H03K19/01728 , H03K19/096
摘要： An output clock signal of a driver 11 charges load capacitance CLto a specific voltage.
Boosting circuit 21 has a boosting capacitance CB one end 13 of which is arranged for receiving a clock signal φ, delayed from the output clock signal of driver 11. A charging circuit for CB comprises voltage supply line 24 and transistor Q3, so CB does not load driver 11. A gate circuit comprising transistor Q1 is provided between boosting capacitor CB and the load capacitance CL. A gate control circuit opens transistor Q1, so that charges can pass from CB to CL to boost the voltage of CL, when a clock signal φ is received. When CL is being discharged the gate control circuit closes transistor Q1. The gate control circuit includes an auxiliary capacitor CG, a transistor Q2 and voltage line 24. CG is charged from the driver 11 through Q2 and when clock signal A is received the voltage of CG, which is applied to the gate of Q1, is raised to open Q1.
摘要翻译：驱动器11的输出时钟信号将负载电容CL充电到特定电压。升压电路21具有升压电容CB，其一端13被布置为接收从驱动器11的输出时钟信号延迟的时钟信号phi。用于CB的充电电路包括电压供给线24和晶体管Q3 因此CB不加载驱动器11.包括晶体管Q1的门电路设置在升压电容器CB和负载电容CL之间。门控制电路打开晶体管Q1，使得当接收到时钟信号时，电荷可以从CB传递到CL以升高CL的电压。当CL放电时，门控电路关闭晶体管Q1。门控电路包括辅助电容器CG，晶体管Q2和电压线24.从驱动器11通过Q2对CG进行充电，并且当接收到时钟信号phi时，施加到Q1的栅极的CG的电压被升高打开Q1。

16. 发明授权

EP3998705B1 DELAY CIRCUIT AND DELAY STRUCTURE 有权
公开(公告)号：EP3998705B1
公开(公告)日：2024-07-10
申请号：EP21777918.0
申请日：2021-06-01
IPC分类号： H03K5/13 , H03K5/134 , H03K5/00
CPC分类号： H03K5/134 , H03K2005/0019520130101 , H03K2005/0012320130101 , H03K5/00 , H03K5/13

17. 发明授权

EP2810177B1 INPUT CAPTURE PERIPHERAL WITH GATING LOGIC 有权
公开(公告)号：EP2810177B1
公开(公告)日：2018-08-01
申请号：EP13703304.9
申请日：2013-01-31
申请人： Microchip Technology Incorporated
发明人： BOWLING, Stephen , USBARTLING, James E.
IPC分类号： G06F13/24 , G04F10/10
CPC分类号： H03K5/00 , G04F10/005 , G04F10/105 , G06F1/02 , G06F3/00 , G06F13/24 , G06F15/00 , G06F17/50
摘要： A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

18. 发明公开

EP2810177A1 INPUT CAPTURE PERIPHERAL WITH GATING LOGIC 有权
标题翻译： EINGABEERFASSUNGSPERIPHERIEVORRICHTUNG麻省理工学院SCHALTUNGSLOGIK
公开(公告)号：EP2810177A1
公开(公告)日：2014-12-10
申请号：EP13703304.9
申请日：2013-01-31
申请人： Microchip Technology Incorporated
发明人： BOWLING, Stephen , USBARTLING, James E.
IPC分类号： G06F13/24 , G04F10/10
CPC分类号： H03K5/00 , G04F10/005 , G04F10/105 , G06F1/02 , G06F3/00 , G06F13/24 , G06F15/00 , G06F17/50
摘要： A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.
摘要翻译：微控制器具有输入捕捉外设，其中所述输入捕捉外围设备被配置为将相关定时器的定时器值存储在存储器中，并且其中所述输入捕捉外设具有控制输入捕捉功能是否被激活的门控输入。

19. 发明公开

EP2787508A1 DRIVE CIRCUIT, SHIFT REGISTER, GATE DRIVE, ARRAY SUBSTRATE AND DISPLAY DEVICE 有权
标题翻译： TREIBERSCHALTUNG，SCHIEBEREGISTER，GATEANSTEUERUNG，ARRAYSUBSTRAT UND ANZEIGEVORRICHTUNG
公开(公告)号：EP2787508A1
公开(公告)日：2014-10-08
申请号：EP12790779.8
申请日：2012-11-09
申请人： BOE Technology Group Co., Ltd. , Hefei BOE Optoelectronics Technology Co., Ltd.
发明人： MA, Rui , SHAO, Xianjie , WANG, Guolei , HU, Ming , LIM, Byung Cheon , TU, Zhizhong
IPC分类号： G11C19/28
CPC分类号： G11C19/28 , H03K5/00
摘要： The disclosure relates to the field of liquid crystal display, and provides a driving circuit, a shifting register, a gate driver, an array substrate and a display device. The driving circuit comprises a pull-up module, a first pull-down module, a second pull-down module, a pull-up driving module, a pull-down driving module and a resetting module, wherein the first pull-down module outputs a switching-off signal to the output terminal according to a signal input from the clock retarding signal input terminal and a signal at a pull-down node; a second pull-down module, when the signal input from the signal input terminal is at a low level, outputs a switching-off signal to the pull-up node and the output terminal according to a signal input from a clock signal input terminal; wherein when the signal input from the signal input terminal is at a high level, the signal input from the clock retarding signal input terminal is also at a high level, and the signal input from the clock signal input terminal and that input from the clock retarding signal input terminal are opposite in phase. The driving circuit according to the disclosure can effectively remove the defect of the threshold voltage drifting due to the gate being applied to a bias voltage stress, and can also decrease the noise of the output voltage.
摘要翻译：本公开涉及液晶显示领域，并提供驱动电路，移位寄存器，栅极驱动器，阵列基板和显示装置。驱动电路包括上拉模块，第一下拉模块，第二下拉模块，上拉驱动模块，下拉驱动模块和复位模块，其中第一下拉模块输出根据从时钟延迟信号输入端子输入的信号和在下拉节点处的信号到输出端子的断开信号; 第二下拉模块，当从所述信号输入端子输入的信号为低电平时，根据从时钟信号输入端子输入的信号，向所述上拉节点和所述输出端子输出关断信号; 其中，当从信号输入端子输入的信号处于高电平时，从时钟延迟信号输入端子输入的信号也处于高电平，从时钟信号输入端输入的信号和从时钟延迟信号输入的信号信号输入端子相位相反。根据本公开的驱动电路可以有效地消除由于栅极被施加到偏置电压应力上的阈值电压漂移的缺陷，并且还可以降低输出电压的噪声。

20. 发明公开

EP0447729A3 Comparateur à seuil immunisé contre le bruit 失效
标题翻译：水平检测器加强了噪声
公开(公告)号：EP0447729A3
公开(公告)日：1992-05-06
申请号：EP90403391.7
申请日：1990-11-29
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Smith, Alan
IPC分类号： G01R19/17
CPC分类号： H03K5/00 , G01R19/16528
摘要： L'invention concerne un comparateur à seuil destiné notamment au comptage de dépassement de niveau d'un signal périodique alternatif. Pour éviter des faux comptages dus aux fluctuations de potentiels d'alimentation et de masse, on prévoit selon l'invention un comparateur à double seuil constitué par un premier inverseur (T1, T′1) et un deuxième inverseur (T2, T′2) recevant le signal à détecter à travers une capacité (C). Les entrées réunies de ces inverseurs sont polarisées par une source de tension de polarisation Vbias fournie par un troisième inverseur (T3, T′3) dont la sortie est rebouclée sur l'entrée. Les géométries des transistors de ces trois inverseurs sont choisies de la manière suivante: le rapport entre les géométries des deux transistors du premier inverseur est légèrement différent du rapport correspondant pour le deuxième inverseur, et le rapport pour le troisième inverseur est compris entre les deux premiers. Cela permet d'avoir deux seuils de basculement proches qui immunisent le comparateur contre les bruits.

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