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11. 发明公开

EP1800314A2 MEMORY USING MIXED VALENCE CONDUCTIVE OXIDES 审中-公开
标题翻译：混合价导电氧化物MEMORY
公开(公告)号：EP1800314A2
公开(公告)日：2007-06-27
申请号：EP05794930.7
申请日：2005-09-01
申请人： UNITY SEMICONDUCTOR CORPORATION
发明人： RINERSON, Darrell , CHEVALLIER, Christophe, J. , KINNEY, Wayne , LAMBERTSON, Roy , LONGCOR, Steven, W. , SANCHEZ, John, E., Jr. , SCHLOSS, Lawrence , SWAB, Philip, F., S. , WARD, Edmond, R.
IPC分类号： G11C16/02 , H01L45/00
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： A multi-level cell memory device, comprising at least one memory element (500, 700) including a first electrode (515), a second electrode (520) , a mixed valence conductive oxide (510, 635, 710) in contact with the first electrode, the mixed valence conductive oxide including a crystalline structure and including mobile oxygen ions (O-), and an electrolytic tunnel barrier (505, 705) in contact with the mixed valence conductive oxide and the second electrode, the electrolytic tunnel barrier having a thickness less than 50 Å. Each memory element is operative to store multiple bits of non-volatile data as a plurality of distinct resistive states that can be non-destructively determined by applying a read voltage pulse across its respective first and second terminals during a read operation. Each memory element is also operative to reversibly switch between the plurality of distinct resistive states by applying a write voltage pulse across its respective first and second terminals during a write operation, the write voltage pulse is operative to generate an electric field in the memory element. The electric field is operative to cause transport of mobile oxygen ions between the mixed valence conductive oxide and the electrolytic tunnel barrier, and the transport is operative to switch one of the plurality of distinct resistive states to another one of the plurality of distinct resistive states.

12. 发明公开

EP1398794A2 Data storage device 审中-公开
标题翻译：数据存储设备
公开(公告)号：EP1398794A2
公开(公告)日：2004-03-17
申请号：EP03255478.4
申请日：2003-09-02
申请人： Hewlett-Packard Development Company, L.P.
发明人： Sharma, Manish , Tran, Lung T.
IPC分类号： G11C11/56 , G11C11/16
CPC分类号： G11C11/56 , G11C11/1673 , G11C11/5607 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/005
摘要： A data storage device (110) includes a resistive cross point array (112) of memory cells (114), each memory cell (114) including serially-connected first and second resistive devices (10, 20) each resistive device having programmable first and second resistance states. The data storage device further includes pluralities of first, second and third conductors (116), and a read circuit (126). Each first conductor (118) is connected to data layers of a column of the first magnetoresistive devices (10, 20); each second conductor )120) is connected to data layers of a column of second magnetoresistive devices (10, 20); and each third conductor (116) is between reference layers of a row of first and second magnetoresistive devices (10, 20). The read circuit (126) applies different first and second voltages during read operations. The first voltage is applied to the first and second conductors (120) crossing a selected memory cell (114); and the second voltage is applied to the third conductor (116) crossing the selected memory cell (114).
摘要翻译：数据存储装置（110）包括存储单元（114）的电阻交叉点阵列（112），每个存储单元（114）包括串联的第一和第二电阻器件（10,20），每个电阻器件具有可编程的第一和第二电阻器件第二电阻状态。数据存储装置还包括多个第一，第二和第三导体（116）以及读取电路（126）。每个第一导体（118）连接到一列第一磁阻器件（10,20）的数据层; 每个第二导体120）连接到一列第二磁阻器件（10,20）的数据层; 并且每个第三导体（116）位于一排第一和第二磁阻器件（10,20）的参考层之间。读取电路（126）在读取操作期间施加不同的第一和第二电压。第一电压施加到与选定存储单元（114）交叉的第一和第二导体（120）; 并且第二电压被施加到与选定存储器单元（114）交叉的第三导体（116）。

13. 发明公开

EP3324412A1 RESISTIVE NON-VOLATILE MEMORY AND A METHOD FOR SENSING A MEMORY CELL IN A RESISTIVE NON-VOLATILE MEMORY 审中-公开
公开(公告)号：EP3324412A1
公开(公告)日：2018-05-23
申请号：EP17197333.2
申请日：2017-10-19
申请人： NXP USA, Inc.
发明人： ROY, Anirban , SADD, Michael A.
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/062 , G11C11/1673 , G11C11/4091 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C2013/005 , G11C2013/0057 , G11C2207/068 , G11C2213/15 , G11C2213/79
摘要： A memory device includes a sense amplifier coupled to a first read voltage during a first phase of a read operation and a second read voltage during a second phase of the read operation. A first and second bias voltages are based on the first and second read voltages and corresponding current on a bit line. A first capacitor includes a terminal coupled to the first and second bias voltages. A first amplifier includes an input coupled to another terminal of the first capacitor and another input coupled to a common mode voltage during the first phase and to a reference voltage during the second phase. A second capacitor includes a terminal coupled to an output of the first amplifier. A second amplifier includes an inverting input coupled to another terminal of the second capacitor and another input coupled to a common mode voltage.

14. 发明公开

EP3244417A1 MAGNETIC RANDOM ACCESS MEMORY (MRAM) AND METHOD OF OPERATION 有权
标题翻译：磁随机存取存储器（MRAM）和操作方法
公开(公告)号：EP3244417A1
公开(公告)日：2017-11-15
申请号：EP17154381.2
申请日：2017-02-02
申请人： NXP USA, Inc.
发明人： Baker Jr, Frank Kelsey , Sadd, Michael A. , Roy, Anirban , Morton, Bruce
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/005 , G11C2213/74 , G11C2213/79
摘要： A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.
摘要翻译：存储装置包括具有第一晶体管，第二晶体管和电阻存储元件的第一存储单元。在读取操作期间，感测电流通过第二晶体管传导并且第一晶体管用于感测电阻存储元件的第一端子处的反馈电压。在写入操作期间，电流通过第一和第二晶体管传导。

15. 发明公开

EP2981895A4 RRAM, AND METHODS OF STORING AND RETRIEVING INFORMATION FOR RRAM 有权
标题翻译：瑞士联邦共和国卢旺达维和部队
公开(公告)号：EP2981895A4
公开(公告)日：2016-11-30
申请号：EP14778923
申请日：2014-02-25
申请人： MICRON TECHNOLOGY INC
发明人： JOHNSON ADAM
IPC分类号： G11C13/00 , G11C29/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C29/74 , G11C2013/005 , G11C2013/0088 , G11C2213/32 , G11C2213/79
摘要： Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
摘要翻译：一些实施例包括存储和检索用于RRAM阵列的数据的方法。该阵列被细分成多个存储器位，每个存储器位具有至少两个存储单元。通过同时改变存储器位内的所有存储单元的电阻状态来编程存储器位。通过确定存储器位内的所有存储单元的求和电流来读取存储器位。一些实施例包括具有多个存储器单元的RRAM。每个存储器单元通过位线/字线组合唯一地寻址。存储器位包含耦合在一起的多个存储器单元，每个存储器位中的耦合存储单元彼此处于相同的电阻状态。

16. 发明公开

EP2684193A4 CELL-STATE DETERMINATION IN PHASE-CHANGE MEMORY 有权转让
标题翻译： CELL地位确定在相变存储器
公开(公告)号：EP2684193A4
公开(公告)日：2014-11-05
申请号：EP12755289
申请日：2012-02-24
申请人： IBM
发明人： PANTAZI ANGELIKI , PAPANDREOU NIKOLAOS , POZIDIS CHARALAMPOS , SEBASTIAN ABU , FREY URS
IPC分类号： G11C13/00 , G11C11/56 , G11C27/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2013/005
摘要： A method, an apparatus, and a device for determining the state of a phase-change memory cell. The method includes the steps of: biasing a cell with a time-varying read voltage (Vread); making a measurement (TM) that satisfies a predetermined condition where the predetermined condition depends on a cell current when the read voltage is applied; and determining a state of the cell based on the measurement.

17. 发明公开

EP2689423A1 RESISTANCE-CHANGE MEMORY 有权
标题翻译： WIDERSTANDSÄNDERUNGSSPEICHER
公开(公告)号：EP2689423A1
公开(公告)日：2014-01-29
申请号：EP11861820.6
申请日：2011-09-16
申请人： Kabushiki Kaisha Toshiba, Inc.
发明人： ICHIHARA, Reika , MATSUSHITA, Daisuke , FUJII, Shosuke
IPC分类号： G11C13/00 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0097 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/33 , H01L27/101 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/148
摘要： According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元和控制电路。存储单元包括第一和第二电极以及设置在第一电极和第二电极之间的可变电阻层。控制电路在第一电极和第二电极之间施加电压以进行写入，擦除和读取。在写入期间，控制电路在第一电极和第二电极之间施加第一电压脉冲，然后在施加第一电压脉冲之后施加与第一电压脉冲不同极性的第二电压脉冲。

18. 发明公开

EP3371810A1 APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME 有权
公开(公告)号：EP3371810A1
公开(公告)日：2018-09-12
申请号：EP16862719.8
申请日：2016-10-25
申请人： Micron Technology, Inc.
发明人： TORTORELLI, Innocenzo , TANG, Stephen , PAPAGIANNI, Christina
IPC分类号： G11C7/10 , G11C7/06
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/005 , G11C2013/0052 , G11C2013/0073 , G11C2213/76 , G11C2213/77
摘要： Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

19. 发明授权

EP2689423B1 RESISTANCE-CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：EP2689423B1
公开(公告)日：2018-01-24
申请号：EP11861820.6
申请日：2011-09-16
申请人： Toshiba Memory Corporation
发明人： ICHIHARA, Reika , MATSUSHITA, Daisuke , FUJII, Shosuke
IPC分类号： G11C13/00 , H01L27/105 , H01L45/00 , H01L49/00 , H01L27/10
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0097 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/33 , H01L27/101 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/148
摘要： According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

20. 发明公开

EP2351083A4 A SILICON BASED NANOSCALE CROSSBAR MEMORY 有权
标题翻译：纳米级交叉存储ON硅基
公开(公告)号：EP2351083A4
公开(公告)日：2014-08-13
申请号：EP09822530
申请日：2009-10-20
申请人： UNIV MICHIGAN
发明人： LU WEI , JO SUNG HYUN , KIM KUK-HWAN
IPC分类号： H01L27/115 , H01L21/8247 , H01L27/24
CPC分类号： H01L45/1253 , B82Y10/00 , B82Y30/00 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2013/0071 , G11C2213/11 , G11C2213/33 , G11C2213/77 , G11C2213/81 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/1608 , H01L45/1675

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