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11. 发明公开

EP2899636A1 A method for testing an Arithmetic logic unit of a flight control system 有权转让
标题翻译： Einem Flugsteuerungssystem中的Testisfahrenfüreine Arithmetisch-logische Einheit
公开(公告)号：EP2899636A1
公开(公告)日：2015-07-29
申请号：EP15159168.2
申请日：2010-07-20
申请人： Honeywell International Inc.
发明人： Bickler, Jason , Brack, Karen
IPC分类号： G06F11/22 , G06F7/499 , G06F7/527 , G06F7/57
CPC分类号： G06F17/11 , G06F7/49921 , G06F7/527 , G06F7/57 , G06F11/2226
摘要： An arithmetic logic unit (ALU) (100) for use within a flight control system is provided. The ALU (100) comprises a first register (110) configured to receive a first operand, a second register (111) configured to receive a second operand, and an adder (130) coupled to the first register (110) and the second register (111). The adder (130) is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.
摘要翻译：提供了一种用于飞行控制系统内的算术逻辑单元（ALU）（100）。 ALU（100）包括被配置为接收第一操作数的第一寄存器（110），被配置为接收第二操作数的第二寄存器（111）和耦合到第一寄存器（110）和第二寄存器（111）。加法器（130）被配置为产生第一操作数和第二操作数的和，并且生成用于确定第一操作数和第二操作数的乘积的中间和。

12. 发明授权

EP2282261B1 Arithmetic logic unit for use within a flight control system 有权转让
标题翻译：一种用于在飞行控制系统中使用的算术逻辑单元
公开(公告)号：EP2282261B1
公开(公告)日：2015-04-29
申请号：EP10170206.6
申请日：2010-07-20
申请人： Honeywell International Inc.
发明人： Bickler, Jason , Brack, Karen
IPC分类号： G06F7/57 , G06F7/499 , G06F7/527
CPC分类号： G06F17/11 , G06F7/49921 , G06F7/527 , G06F7/57 , G06F11/2226

13. 发明授权

EP1819049B1 Specialized processing block for programmable logic device 有权转让
标题翻译：用于可编程逻辑器件的专门处理块
公开(公告)号：EP1819049B1
公开(公告)日：2012-09-26
申请号：EP06024743.4
申请日：2006-11-29
申请人： Altera Corporation
发明人： Langhammer, Martin , Lee, Kwan, Yee, Martin , Azgomi, Orang , Streicher, Keone , Lin, Yi-Wen
IPC分类号： H03K19/177 , G06F7/527
CPC分类号： H03K19/17732 , G06F7/527 , G06F7/5272

14. 发明公开

EP1819049A1 Specialized processing block for programmable logic device 有权转让
标题翻译： Spezialisierter Verarbeitungsblockfürprogrammierbare logischeGeräte
公开(公告)号：EP1819049A1
公开(公告)日：2007-08-15
申请号：EP06024743.4
申请日：2006-11-29
申请人： Altera Corporation
发明人： Langhammer, Martin , Lee, Kwan, Yee, Martin , Azgomi, Orang , Streicher, Keone , Lin, Yi-Wen
IPC分类号： H03K19/177 , G06F7/527
CPC分类号： H03K19/17732 , G06F7/527 , G06F7/5272
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译：用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。专用处理块还具有输入和输出级以及回送功能，以允许块被配置用于各种数字信号处理操作。

15. 发明公开

EP1078461A1 SCHALTUNGSANORDNUNG MIT EINZELELEKTRON-BAUELEMENTEN UND VERFAHREN ZU DEREN BETRIEB 有权
标题翻译：个别电子组件的电路和方法操作
公开(公告)号：EP1078461A1
公开(公告)日：2001-02-28
申请号：EP99919077.0
申请日：1999-03-15
申请人： Infineon Technologies AG
发明人： RÖSNER, Wolfgang , RAMCKE, Ties , RISCH, Lothar
IPC分类号： H03K19/08
CPC分类号： G06F7/527 , B82Y10/00 , G06F7/502 , G06F7/505 , G06F2207/4828 , H03K19/08 , Y10S977/936 , Y10S977/937 , Y10S977/94
摘要： A circuit with at least five individual electron transistors, whereby three of said transistors (ET1, ET2, ET3) are mounted between a first main node (H1) and an output (A) via a second main node (H2) and a third main node (H3). The fourth individual electron transistor (ET4) is mounted between the second main node and a first supply voltage (V1), whereby the gate electrode pertaining thereto (G4) is connected to the first main node (H1). The fifth individual electron transistor (ET5) is mounted between the third main node (H3) and the first supply voltage (VI), whereby the gate electrode (G5) pertaining thereto is connected to the second main node (H2). The circuit is suitable for use as a full loader and a multiplier.

16. 发明公开

EP1038216A1 IMPLEMENTATION OF MULTIPLIERS IN PROGRAMMABLE ARRAYS 无效
标题翻译：现场可编程阵列中的多路复用器
公开(公告)号：EP1038216A1
公开(公告)日：2000-09-27
申请号：EP98960041.6
申请日：1998-12-16
申请人： Hewlett-Packard Company
发明人： MARSHALL, Alan David , STANSFIELD, Anthony , VUILLEMIN, Jean
IPC分类号： G06F7/52
CPC分类号： G06F7/527 , G06F7/53 , G06F7/5338 , G06F9/3017 , G06F9/30181 , G06F15/7867
摘要： Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided a method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein said processing devices and an input for the first number and an input for the second number are interconnected by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device: the value received at the instruction input is determined by one or more bits of the first number; data inputs are provided by m bits of the second number, and, if appropriate, a carry input to add a carry from a less significant partial product and/or a summation input to sum all the partial products of the same significance; data outputs are provided as a summation output containing the least significant m bits of the partial product and a carry output containing any more significant bits of the partial product.

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